From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 16:54:19 +0000 (-0800)
Subject: RAM64M8 to also have [5:0] for address
X-Git-Tag: working-ls180~921^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6514fc2e13976b15be396f413b046deb6f0c9fa;p=yosys.git

RAM64M8 to also have [5:0] for address
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 56eb782c6..f9ce496ff 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1230,14 +1230,14 @@ module RAM64M8 (
   output DOF,
   output DOG,
   output DOH,
-  input [4:0] ADDRA,
-  input [4:0] ADDRB,
-  input [4:0] ADDRC,
-  input [4:0] ADDRD,
-  input [4:0] ADDRE,
-  input [4:0] ADDRF,
-  input [4:0] ADDRG,
-  input [4:0] ADDRH,
+  input [5:0] ADDRA,
+  input [5:0] ADDRB,
+  input [5:0] ADDRC,
+  input [5:0] ADDRD,
+  input [5:0] ADDRE,
+  input [5:0] ADDRF,
+  input [5:0] ADDRG,
+  input [5:0] ADDRH,
   input DIA,
   input DIB,
   input DIC,