From: Gabe Black <gabeblack@google.com>
Date: Tue, 20 Nov 2018 01:55:37 +0000 (-0800)
Subject: base: arch: Get rid of the now unused FloatRegVal type.
X-Git-Tag: v19.0.0.0~1227
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d65f3f9a846b65d6a1596aa143a555bd0d4287ab;p=gem5.git

base: arch: Get rid of the now unused FloatRegVal type.

This type is no longer used since FP registers are accessed as integer
bit patterns.

Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f
Reviewed-on: https://gem5-review.googlesource.com/c/14459
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
---

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 2bff11b5c..6c71320b6 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -48,7 +48,6 @@ const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 typedef RegVal IntReg;
 
 // floating point register file entry type
-typedef FloatRegVal FloatReg;
 typedef RegVal FloatRegBits;
 
 // control register file contents
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index d2095d84d..6f7097b08 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -282,7 +282,6 @@ typedef RegVal IntReg;
 
 // floating point register file entry type
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 
 // cop-0/cop-1 system control register
 typedef RegVal MiscReg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 527193cc4..fb815af4a 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -48,7 +48,6 @@ namespace NullISA {
 
 typedef RegVal IntReg;
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg;
 typedef RegVal MiscReg;
 const RegIndex ZeroReg = 0;
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 39f7d34f8..989b4c52a 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -49,7 +49,6 @@ typedef RegVal IntReg;
 
 // Floating point register file entry type
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef RegVal MiscReg;
 
 // dummy typedef since we don't have CC regs
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 75f74ef2d..2de154e22 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -65,7 +65,6 @@ const int MaxMiscDestRegs = 1;
 
 typedef RegVal IntReg;
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg; // Not applicable to Riscv
 typedef RegVal MiscReg;
 
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a2a74cc4a..509f7a111 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -105,7 +105,6 @@ constexpr unsigned NumVecRegs = 1;
 
 //These floating point types are correct for mmx, but not
 //technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef FloatRegVal FloatReg;
 typedef RegVal FloatRegBits;
 
 } // namespace X86ISA
diff --git a/src/base/types.hh b/src/base/types.hh
index c02a606cf..d99384529 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -166,7 +166,6 @@ isRomMicroPC(MicroPC upc)
 const Addr MaxAddr = (Addr)-1;
 
 typedef uint64_t RegVal;
-typedef double FloatRegVal;
 
 static inline uint32_t
 floatToBits32(float val)