From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Dec 2019 03:21:42 +0000 (-0800)
Subject: Add assertion
X-Git-Tag: working-ls180~881^2^2~104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d66d06b91df4aade84107b59b2b1f32188a3995e;p=yosys.git

Add assertion
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 5139cb80b..5b4100574 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1107,6 +1107,7 @@ struct Abc9Pass : public Pass {
 					Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
 					if (abc9_clock_wire == NULL)
 						log_error("'%s.$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+					log_assert(GetSize(abc9_clock_wire) == 1);
 					SigBit abc9_clock = sigmap(abc9_clock_wire);
 					auto r = clocks.insert(abc9_clock.wire);
 					if (r.second) {