From: lkcl Date: Thu, 8 Sep 2022 15:14:45 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~617 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d670171d3edcd5705764e319681bfe472ef95e35;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index b9385b669..487774576 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -119,3 +119,4 @@ document. The primary options are: [^extend]: Prefix opcode space **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations. +[^pseudorewrite] elwidth overrides does however mean that all SFS / SFFS pseudocode will need rewriting to be in terms of XLEN. This has the indirect side-effect of automatically making a 32-bit Scalar Power ISA Specification possible, as well as a future 128-bit one (Cross-reference: RISC-V RV32 and RV128)