From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 18:26:55 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_arrival
X-Git-Tag: working-ls180~1075^2^2~36
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_arrival
---

d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5
diff --cc techlibs/ecp5/cells_sim.v
index 24de0c3c2,dc8334acb..e2bf3c854
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@@ -113,7 -118,8 +115,8 @@@ module TRELLIS_DPR16X4 
  	input        WRE,
  	input        WCK,
  	input  [3:0] RAD,
- 	/* (* abc_arrival=<TODO> *) */ output [3:0] DO
 -	output [3:0] DO
++	/* (* abc_arrival=<TODO> *) */
++    output [3:0] DO
  );
  	parameter WCKMUX = "WCK";
  	parameter WREMUX = "WRE";
diff --cc techlibs/xilinx/cells_sim.v
index 65c59759a,3ad96d7fb..21ac19300
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -297,11 -297,13 +299,12 @@@ module FDPE_1 ((* abc_arrival=303 *) ou
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
 -(* abc_box_id = 5 *)
  module RAM32X1D (
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
++  (* abc_arrival=1153 *)
+   output DPO, SPO,
 -  (* abc_scc_break *)
    input  D,
    input  WCLK,
 -  (* abc_scc_break *)
    input  WE,
    input  A0, A1, A2, A3, A4,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
@@@ -317,11 -319,13 +320,12 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
 -(* abc_box_id = 6 *)
  module RAM64X1D (
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
++  (* abc_arrival=1153 *)
+   output DPO, SPO,
 -  (* abc_scc_break *)
    input  D,
    input  WCLK,
 -  (* abc_scc_break *)
    input  WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@@ -337,11 -341,13 +341,12 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
 -(* abc_box_id = 7 *)
  module RAM128X1D (
 -  output       DPO, SPO,
 -  (* abc_scc_break *)
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
++  (* abc_arrival=1153 *)
++  output DPO, SPO,
    input        D,
    input        WCLK,
 -  (* abc_scc_break *)
    input        WE,
    input  [6:0] A, DPRA
  );