From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 20:40:17 +0000 (-0800)
Subject: abc9 to use & syntax for -fast, and name fixes
X-Git-Tag: working-ls180~1237^2~295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6b317b349894d0837018dde28eb46eff55c4ce8;p=yosys.git

abc9 to use & syntax for -fast, and name fixes
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index e85cf48e1..94fbffeaf 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -37,7 +37,7 @@
 
 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
-#define ABC_FAST_COMMAND_LUT "strash; dretime; if"
+#define ABC_FAST_COMMAND_LUT "&st; &retime; &if"
 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
 
@@ -588,7 +588,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 						if (a_bit.wire->port_input) {
 							// If it's a NOT gate that comes from a primary input directly
 							// then implement it using a LUT
-							cell = module->addLut(remap_name(stringf("%s_lut", c->name.c_str())),
+							cell = module->addLut(remap_name(stringf("%slut", c->name.c_str())),
 									RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
 									RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
 									1);
@@ -599,9 +599,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 							// (TODO: Optimise by not cloning unless will increase depth)
 							RTLIL::IdString driver_name;
 							if (GetSize(a_bit.wire) == 1)
-								driver_name = stringf("%s_lut", a_bit.wire->name.c_str());
+								driver_name = stringf("%slut", a_bit.wire->name.c_str());
 							else
-								driver_name = stringf("%s[%d]_lut", a_bit.wire->name.c_str(), a_bit.offset);
+								driver_name = stringf("%s[%d]lut", a_bit.wire->name.c_str(), a_bit.offset);
 							RTLIL::Cell* driver = mapped_mod->cell(driver_name);
 							log_assert(driver);
 							auto driver_a = driver->getPort("\\A").chunks();
@@ -612,7 +612,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 								if (b == RTLIL::State::S0) b = RTLIL::State::S1;
 								else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
 							}
-							cell = module->addLut(remap_name(stringf("%s_lut", c->name.c_str())),
+							cell = module->addLut(remap_name(stringf("%slut", c->name.c_str())),
 									driver_a,
 									RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
 									driver_lut);