From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 Dec 2018 09:17:36 +0000 (+0000)
Subject: add links
X-Git-Tag: convert-csv-opcode-to-binary~4821
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6c4e0603a97352cca40ec9bbcc6f93b8a5af3ef;p=libreriscv.git

add links
---

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 7922e1897..273d11e83 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -115,6 +115,7 @@ called the flip-flops orchestrating the timing "collectors".
   reservation stations take a *lot* of power.
 * MESI cache protocol, python <https://github.com/sunkarapk/mesi-cache.git>
   <https://github.com/afwolfe/mesi-simulator>
+* <https://github.com/ssc3?tab=repositories> interesting stuff
 * <https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Solution_A._Bypassing>
   pipeline bypassing
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>