From: lkcl Date: Sat, 9 Apr 2022 20:03:47 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2823 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6cd055e73dca51d6476e037a214f134e52b1d6b;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 6a40b9419..c3d5bf52d 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -118,6 +118,15 @@ It is important to note that having a different v3.0B Scalar opcode that is different from an SVP64 one is highly undesirable: the complexity in the decoder is greatly increased. +# EXTRA Field Mapping + +In Power ISA v3.1 prefixing there are bits which describe and classify +the prefix in a fashion that is independent of the suffix. MLSS for +example. For SVP64 there is insufficient space to make the SVP64 Prefix +"self-describing", and consequently every single Scalar instruction +had to be individually analysed, by rote, to craft an EXTRA Field Mapping. +This process was semi-automated and is described in this section. + # Single Predication This is a standard mode normally found in Vector ISAs. every element in every source Vector and in the destination uses the same bit of one single predicate mask.