From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 21:53:28 +0000 (-0800)
Subject: abc9_ops: still emit delay table even box has no timing
X-Git-Tag: working-ls180~780^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6cff777513ff5b470bcd37588c123e118ad0cdb;p=yosys.git

abc9_ops: still emit delay table even box has no timing
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index fc2f52157..8337b61b1 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -669,10 +669,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		ss << std::endl;
 
 		auto &t = timing.setup_module(module).comb;
-		if (t.empty()) {
+		if (t.empty())
 			log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
-			continue;
-		}
 
 		for (const auto &o : outputs) {
 			first = true;