From: Luke Kenneth Casson Leighton Date: Sun, 20 Mar 2022 13:40:47 +0000 (+0000) Subject: crank A7 FPGA speed down to experiment X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6ed8f60b7382bb53496a87f8a79b973bfaca693;p=ls2.git crank A7 FPGA speed down to experiment --- diff --git a/src/arty_a7.py b/src/arty_a7.py index 55ef6ed..4091072 100644 --- a/src/arty_a7.py +++ b/src/arty_a7.py @@ -9,7 +9,7 @@ from arty_crg import ArtyA7CRG class BlinkyClocked(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules.crg = ArtyA7CRG(25e6) + m.submodules.crg = ArtyA7CRG(12e6) m.submodules.blinky = Blinky() return m diff --git a/src/ls2.py b/src/ls2.py index 5e0997d..855ddd3 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -589,7 +589,7 @@ if __name__ == "__main__": if fpga == 'versa_ecp5_85': clk_freq = 55e6 if fpga == 'arty_a7': - clk_freq = 25e6 + clk_freq = 12e6 # select a firmware file firmware = None