From: Andrey Miroshnikov Date: Thu, 18 Nov 2021 22:53:25 +0000 (+0000) Subject: Added jtagutils and openpower state dependency for borrowed jtag test cases, see... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d6f4066d9aef1f84f1a1e0b885739e57b2e17710;p=pinmux.git Added jtagutils and openpower state dependency for borrowed jtag test cases, see bug #50 --- diff --git a/src/spec/dmi.py b/src/spec/dmi.py index 4d89769..52a00c4 100644 --- a/src/spec/dmi.py +++ b/src/spec/dmi.py @@ -10,7 +10,7 @@ from nmigen import Elaboratable, Module, Signal, Cat, Const, Record, Array, Mux from nmutil.iocontrol import RecordObject from nmigen.utils import log2_int from nmigen.cli import rtlil -from soc.config.state import CoreState +from state import CoreState # DMI register addresses diff --git a/src/spec/jtagutils.py b/src/spec/jtagutils.py new file mode 100644 index 0000000..a642bd1 --- /dev/null +++ b/src/spec/jtagutils.py @@ -0,0 +1,223 @@ +#The server code +import socket +from socket import close, AF_INET, SOCK_STREAM +import sys +import select +import time + + +def client_sync(dut): + tck = yield dut.cbus.tck + tms = yield dut.cbus.tms + tdi = yield dut.cbus.tdi + dut.c.jtagremote_client_send((tck, tms, tdi)) + #print ("about to client recv") + while True: + tdo = dut.c.jtagremote_client_recv(timeout=0) + if tdo is not None: + break + yield + yield dut.cbus.tdo.eq(tdo) + + +def tms_state_set(dut, bits): + for bit in bits: + yield dut.cbus.tms.eq(bit) + yield from client_sync(dut) + yield dut.cbus.tck.eq(1) + yield from client_sync(dut) + yield + yield dut.cbus.tck.eq(0) + yield from client_sync(dut) + yield + yield from client_sync(dut) + yield dut.cbus.tms.eq(0) + yield from client_sync(dut) + + +def tms_data_getset(dut, tms, d_len, d_in=0): + res = 0 + yield dut.cbus.tms.eq(tms) + for i in range(d_len): + tdi = 1 if (d_in & (1< +# Funded by NLnet http://nlnet.nl +"""SVSATE SPR Record. actually a peer of PC (CIA/NIA) and MSR + +https://libre-soc.org/openpower/sv/sprs/ + +| Field | Name | Description | +| ----- | -------- | --------------------- | +| 0:6 | maxvl | Max Vector Length | +| 7:13 | vl | Vector Length | +| 14:20 | srcstep | for srcstep = 0..VL-1 | +| 21:27 | dststep | for dststep = 0..VL-1 | +| 28:29 | subvl | Sub-vector length | +| 30:31 | svstep | for svstep = 0..SUBVL-1 | +| 32:33 | mi0 | REMAP RA SVSHAPE0-3 | +| 34:35 | mi1 | REMAP RB SVSHAPE0-3 | +| 36:37 | mi2 | REMAP RC SVSHAPE0-3 | +| 38:39 | mo0 | REMAP RT SVSHAPE0-3 | +| 40:41 | mo1 | REMAP EA SVSHAPE0-3 | +| 42:46 | SVme | REMAP enable (RA-RT) | +| 47:61 | rsvd | reserved | +| 62 | RMpst | REMAP persistence | +| 63 | vfirst | Vertical First mode | +""" + +from nmigen import Signal, Record + + +# In nMigen, Record order is from LSB to MSB +# but Power ISA specs are all MSB to LSB (MSB0). +class SVSTATERec(Record): + layout = [("vfirst", 1), + ("RMpst", 1), + ("rsvd", 15), + ("SVme", 5), + ("mo1", 2), + ("mo0", 2), + ("mi2", 2), + ("mi1", 2), + ("mi0", 2), + ("svstep", 2), + ("subvl", 2), + ("dststep", 7), + ("srcstep", 7), + ("vl", 7), + ("maxvl", 7), + ] + + def __init__(self, name=None): + super().__init__(name=name, layout=SVSTATERec.layout)