From: Hyunjun Ko <zzoon@igalia.com>
Date: Fri, 1 Nov 2019 08:34:54 +0000 (+0000)
Subject: freedreno/ir3: Add cat4 mediump opcodes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d70192e6973aec3bbe2be70192f18b6a2257872a;p=mesa.git

freedreno/ir3: Add cat4 mediump opcodes

v2: Reworked to assign half-opcodes in ir3_ra.c (krh).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
---

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index fbe28ac3cc1..c682c6e0db0 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -1463,8 +1463,11 @@ INSTR3(SAD_S32)
 /* cat4 instructions: */
 INSTR1(RCP)
 INSTR1(RSQ)
+INSTR1(HRSQ)
 INSTR1(LOG2)
+INSTR1(HLOG2)
 INSTR1(EXP2)
+INSTR1(HEXP2)
 INSTR1(SIN)
 INSTR1(COS)
 INSTR1(SQRT)
diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index 5a63e77c89e..f04db4f29ac 100644
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1110,6 +1110,21 @@ static void fixup_half_instr_dst(struct ir3_instruction *instr)
 			break;
 		}
 		break;
+	case 4:
+		switch (instr->opc) {
+		case OPC_RSQ:
+			instr->opc = OPC_HRSQ;
+			break;
+		case OPC_LOG2:
+			instr->opc = OPC_HLOG2;
+			break;
+		case OPC_EXP2:
+			instr->opc = OPC_HEXP2;
+			break;
+		default:
+			break;
+		}
+		break;
 	case 5:
 		instr->cat5.type = half_type(instr->cat5.type);
 		break;