From: Martin Hunt Date: Thu, 29 Aug 1996 00:35:11 +0000 (+0000) Subject: Wed Aug 28 17:33:19 1996 Martin M. Hunt X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d70b4d426ba96845c0a40138c5d3ee05ac279ca5;p=binutils-gdb.git Wed Aug 28 17:33:19 1996 Martin M. Hunt * Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems. --- diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index bd788c1b100..a1c8f4e7961 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,22 @@ +Wed Aug 28 17:33:19 1996 Martin M. Hunt + + * Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems. + +Mon Aug 26 18:30:28 1996 Martin M. Hunt + + * d10v_sim.h (SEXT32): Added. + * interp.c: Commented out printfs. + * simops.c: Fixed error in sb and st2w. + +Thu Aug 15 13:30:03 1996 Martin M. Hunt + + * Makefile.in, d10v_sim.h, interp.c, simops.c: Added remaining + DSP instructions. Added modulo addressing. + +Sun Aug 11 12:57:15 1996 Martin M. Hunt + + * Makefile.in, d10v_sim.h, interp.c, simops.c: Snapshot. + Fri Aug 2 17:44:24 1996 Martin M. Hunt * d10v_sim.h, simops.c: Snapshot. diff --git a/sim/d10v/Makefile.in b/sim/d10v/Makefile.in index 393cc61940e..ea296b13f95 100644 --- a/sim/d10v/Makefile.in +++ b/sim/d10v/Makefile.in @@ -56,7 +56,7 @@ INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1 AR = @AR@ AR_FLAGS = rc CC = @CC@ -CFLAGS = @CFLAGS@ +CFLAGS = @CFLAGS@ @DEFS@ MAKEINFO = makeinfo RANLIB = @RANLIB@ CC_FOR_BUILD = @CC_FOR_BUILD@ @@ -77,7 +77,7 @@ CSEARCH = -I. -I$(srcdir) -I../../include \ -I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/sh DEP = mkdep -all: run +all: run libsim.a run: interp.o $(X) run.o table.o callback.o simops.o $(CC) $(CFLAGS) -o run $(X) interp.o table.o callback.o simops.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a $(XL) -lm @@ -86,7 +86,7 @@ interp.o:interp.c table.c run.o:run.c libsim.a:interp.o table.o simops.o - $(AR) $(ARFLAGS) libsim.a interp.o table.o + $(AR) $(ARFLAGS) libsim.a interp.o table.o simops.o $(RANLIB) libsim.a simops.h: gencode @@ -95,7 +95,7 @@ simops.h: gencode table.c: gencode simops.h ./gencode >$@ -gencode: gencode.c +gencode: gencode.c ../../opcodes/libopcodes.a $(CC) $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHE) -o gencode $(srcdir)/gencode.c ../../opcodes/libopcodes.a -lc .c.o: @@ -114,7 +114,7 @@ TAGS: force clean: rm -f *.[oa] *~ core *.E *.p *.ip aout-params.h gen-aout - rm -f run libsim.a + rm -f run table.c simops.h gencode libsim.a distclean mostlyclean maintainer-clean realclean: clean rm -f TAGS diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h index a2b4b2b9467..83c7aeb5598 100644 --- a/sim/d10v/d10v_sim.h +++ b/sim/d10v/d10v_sim.h @@ -81,6 +81,12 @@ extern struct simops Simops[]; /* sign extend a 40 bit number */ #define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL) +/* sign extend a 44 bit number */ +#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL) + +/* sign extend a 60 bit number */ +#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL) + #define MAX32 0x7fffffffLL #define MIN32 0xff80000000LL #define MASK32 0xffffffffLL @@ -93,17 +99,28 @@ extern struct simops Simops[]; #ifdef WORDS_BIGENDIAN -#define RW(x) (*((uint16 *)((x)+State.imem))) -#define RLW(x) (*((uint32 *)((x)+State.imem))) -#define SW(addr,data) RW(addr)=data +#define RW(x) (*((uint16 *)((x)+State.imem))) +#define RLW(x) (*((uint32 *)((x)+State.imem))) +#define SW(addr,data) RW(addr)=data +#define READ_16(x) (*((int16 *)(x))) +#define WRITE_16(addr,data) (*(int16 *)(addr)=data) +#define READ_64(x) (*((int64 *)(x))) +#define WRITE_64(addr,data) (*(int64 *)(addr)=data) #else -uint32 get_longword_swap PARAMS ((uint16 x)); -uint16 get_word_swap PARAMS ((uint16 x)); -void write_word_swap PARAMS ((uint16 addr, uint16 data)); -#define SW(addr,data) write_word_swap(addr,data) -#define RW(x) get_word_swap(x) -#define RLW(x) get_longword_swap(x) +uint32 get_longword PARAMS ((uint8 *)); +uint16 get_word PARAMS ((uint8 *)); +int64 get_longlong PARAMS ((uint8 *)); +void write_word PARAMS ((uint8 *addr, uint16 data)); +void write_longlong PARAMS ((uint8 *addr, int64 data)); + +#define SW(addr,data) write_word((long)(addr)+State.imem,data) +#define RW(x) get_word((long)(x)+State.imem) +#define RLW(x) get_longword((long)(x)+State.imem) +#define READ_16(x) get_word(x) +#define WRITE_16(addr,data) write_word(addr,data) +#define READ_64(x) get_longlong(x) +#define WRITE_64(addr,data) write_longlong(addr,data) #endif /* not WORDS_BIGENDIAN */ diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 279a6cb13ab..20cbdbe99cc 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -1,3 +1,4 @@ +#include #include "sysdep.h" #include "bfd.h" #include "remote-sim.h" @@ -59,30 +60,56 @@ lookup_hash (ins, size) } uint32 -get_longword_swap (x) - uint16 x; +get_longword (x) + uint8 *x; { - uint8 *a = (uint8 *)(x + State.imem); + uint8 *a = x; return (a[0]<<24) + (a[1]<<16) + (a[2]<<8) + (a[3]); } +int64 +get_longlong (x) + uint8 *x; +{ + uint8 *a = x; + return ((int64)a[0]<<56) + ((int64)a[1]<<48) + ((int64)a[2]<<40) + ((int64)a[3]<<32) + + ((int64)a[4]<< 24) + ((int64)a[5]<<16) + ((int64)a[6]<<8) + (int64)a[7]; +} + uint16 -get_word_swap (x) - uint16 x; +get_word (x) + uint8 *x; { - uint8 *a = (uint8 *)(x + State.imem); - return (a[0]<<8) + a[1]; + uint8 *a = x; + return ((uint16)a[0]<<8) + a[1]; } void -write_word_swap (addr, data) - uint16 addr, data; +write_word (addr, data) + uint8 *addr; + uint16 data; { - uint8 *a = (uint8 *)(addr + State.imem); + uint8 *a = addr; a[0] = data >> 8; a[1] = data & 0xff; } +void +write_longlong (addr, data) + uint8 *addr; + int64 data; +{ + uint8 *a = addr; + a[0] = data >> 56; + a[1] = (data >> 48) & 0xff; + a[2] = (data >> 40) & 0xff; + a[3] = (data >> 32) & 0xff; + a[4] = (data >> 24) & 0xff; + a[5] = (data >> 16) & 0xff; + a[6] = (data >> 8) & 0xff; + a[7] = data & 0xff; +} + static void get_operands (struct simops *s, uint32 ins) @@ -127,26 +154,35 @@ do_parallel (ins1, ins2) uint16 ins1, ins2; { struct hash_entry *h1, *h2; - /* printf ("do_parallel %x || %x\n",ins1,ins2); */ + /* printf ("do_parallel %x || %x\n",ins1,ins2); */ h1 = lookup_hash (ins1, 0); - get_operands (h1->ops, ins1); h2 = lookup_hash (ins2, 0); - get_operands (h2->ops, ins2); + if (h1->ops->exec_type == PARONLY) { + get_operands (h1->ops, ins1); (h1->ops->func)(); if (State.exe) - (h2->ops->func)(); + { + get_operands (h2->ops, ins2); + (h2->ops->func)(); + } } else if (h2->ops->exec_type == PARONLY) { + get_operands (h2->ops, ins2); (h2->ops->func)(); if (State.exe) - (h1->ops->func)(); + { + get_operands (h1->ops, ins1); + (h1->ops->func)(); + } } else { + get_operands (h1->ops, ins1); (h1->ops->func)(); + get_operands (h2->ops, ins2); (h2->ops->func)(); } } @@ -190,7 +226,7 @@ sim_write (addr, buffer, size) int i; init_system (); - printf ("sim_write %d bytes to 0x%x\n",size,addr); + /* printf ("sim_write %d bytes to 0x%x\n",size,addr); */ for (i = 0; i < size; i++) { State.imem[i+addr] = buffer[i]; @@ -257,44 +293,50 @@ sim_resume (step, siggnal) int i; reg_t oldpc; - printf ("sim_resume %d %d\n",step,siggnal); +/* printf ("sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */ - while (1) - { - inst = RLW (PC << 2); - oldpc = PC; - switch (inst & 0xC0000000) - { - case 0xC0000000: - /* long instruction */ - do_long (inst & 0x3FFFFFFF); - break; - case 0x80000000: - /* R -> L */ - do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15); - break; - case 0x40000000: - /* L -> R */ - do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); - break; - case 0: - do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); - break; - } - - if (State.RP && PC == RPT_E) - { - RPT_C -= 1; - if (RPT_C == 0) - State.RP = 0; - else - PC = RPT_S; - } - - /* FIXME */ - if (PC == oldpc) - PC++; - } + if (step) + State.exception = SIGTRAP; + else + State.exception = 0; + + do + { + inst = RLW (PC << 2); + oldpc = PC; + switch (inst & 0xC0000000) + { + case 0xC0000000: + /* long instruction */ + do_long (inst & 0x3FFFFFFF); + break; + case 0x80000000: + /* R -> L */ + do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15); + break; + case 0x40000000: + /* L -> R */ + do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); + break; + case 0: + do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); + break; + } + + if (State.RP && PC == RPT_E) + { + RPT_C -= 1; + if (RPT_C == 0) + State.RP = 0; + else + PC = RPT_S; + } + + /* FIXME */ + if (PC == oldpc) + PC++; + } + while (!State.exception); } int @@ -308,7 +350,7 @@ void sim_info (verbose) int verbose; { - printf ("sim_verbose\n"); + printf ("sim_info\n"); } void @@ -341,5 +383,79 @@ sim_stop_reason (reason, sigrc) enum sim_stop *reason; int *sigrc; { - printf ("sim_stop_reason\n"); +/* printf ("sim_stop_reason: PC=0x%x\n",PC<<2); */ + + if (State.exception == SIGQUIT) + { + *reason = sim_exited; + *sigrc = State.exception; + } + else + { + *reason = sim_stopped; + *sigrc = State.exception; + } +} + +void +sim_fetch_register (rn, memory) + int rn; + unsigned char *memory; +{ + if (rn > 31) + { + WRITE_64 (memory, State.a[rn-32]); + /* printf ("sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */ + } + else + { + WRITE_16 (memory, State.regs[rn]); + /* printf ("sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */ + } +} + +void +sim_store_register (rn, memory) + int rn; + unsigned char *memory; +{ + if (rn > 31) + { + State.a[rn-32] = READ_64 (memory) & MASK40; + /* printf ("store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */ + } + else + { + State.regs[rn]= READ_16 (memory); + /* printf ("store: r%d=0x%x\n",rn,State.regs[rn]); */ + } } + +sim_read (addr, buffer, size) + SIM_ADDR addr; + unsigned char *buffer; + int size; +{ + int i; + for (i = 0; i < size; i++) + { + buffer[i] = State.imem[addr + i]; + } + return size; +} + +void +sim_do_command (cmd) + char *cmd; +{ + printf("sim_do_command: %s\n",cmd); +} + +int +sim_load (prog, from_tty) + char *prog; + int from_tty; +{ + /* Return nonzero so GDB will handle it. */ + return 1; +}