From: Hsuan Hsu <hsuan.hsu@mediatek.com>
Date: Fri, 14 Feb 2020 10:32:46 +0000 (+0800)
Subject: cpu-o3: Fix corrupted rename map in vector mode switching
X-Git-Tag: v20.0.0.0~438
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d71076d41ceacdc349874cc3a12573d3a66830bd;p=gem5.git

cpu-o3: Fix corrupted rename map in vector mode switching

This patch fixes the AArch32-AArch64 interprocessing issue introduced in
3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model.

When O3CPU switches vector renaming mode, architectural-physical mapping
and physical free list are switched in the following way so that content
of vectors has no change from software view:

Case 1. Full mode -> Elem mode (AArch64 -> AArch32):
1.1. Split vector-vector mapping into element-element mapping.
1.2. Split vectors in free list into elements.

Case 2. Elem mode -> Full mode (AArch32 -> AArch64):
2.1. Move content of all N*M mapped physical elements to first N*M
     physical elements in architectural order (N = number of
     architectural vectors, M = number of elements per vector).
2.2. Map N architectural vectors to first N physical vectors (i.e.
     initial mapping in full mode).
2.3. Place remaining physical vectors in free list (i.e. initial free
     list in full mode).

Previous gem5 revision misses step 2.2 when AArch32->AArch64 switch.
The wrong mapping will lead to the situation in which a physical vector
is assigned twice to a same architectural vector without being freed.
Once this occurs, the physical vector will not be freed anymore, since
it is treated as a special register (e.g. zero or misc) by O3CPU's
renaming logic. Eventually O3CPU will either stall forever when all
physical vectors get stuck, or trigger the panic condition "The free
list has lost vector registers" when AArch64->AArch32 switch. This patch
adds the missing step and fixes the issue.

Change-Id: I32233635c28763260bcbb776b52ed198a9abace9
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25743
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index fdb98940f..dbea832ef 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -215,5 +215,10 @@ UnifiedRenameMap::switchMode(VecMode newVecMode)
             regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
         }
 
+        auto range = regFile->getRegIds(VecRegClass);
+        for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
+            setEntry(RegId(VecRegClass, i), &(*(range.first + i)));
+        }
+
     }
 }