From: Andreas Hansson Date: Fri, 21 Aug 2015 11:03:21 +0000 (-0400) Subject: ruby: Move Rubys cache class from Cache.py to RubyCache.py X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d71a0d790d8d1113480c5a57d7bfbb9b7d0d0037;p=gem5.git ruby: Move Rubys cache class from Cache.py to RubyCache.py This patch serves to avoid name clashes with the classic cache. For some reason having two 'SimObject' files with the same name creates problems. --HG-- rename : src/mem/ruby/structures/Cache.py => src/mem/ruby/structures/RubyCache.py --- diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 4e01de65b..3e0c21a41 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -37,7 +37,7 @@ from Ruby import send_evicts # # Declare caches used by the protocol # -class Cache(RubyCache): pass +class L1Cache(RubyCache): pass def define_options(parser): return @@ -70,9 +70,9 @@ def create_system(options, full_system, system, dma_ports, ruby_system): # Only one cache exists for this protocol, so by default use the L1D # config parameters. # - cache = Cache(size = options.l1d_size, - assoc = options.l1d_assoc, - start_index_bit = block_size_bits) + cache = L1Cache(size = options.l1d_size, + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py index 7a968a253..eb31b3804 100644 --- a/configs/ruby/Network_test.py +++ b/configs/ruby/Network_test.py @@ -36,7 +36,7 @@ from Ruby import create_topology # # Declare caches used by the protocol # -class Cache(RubyCache): pass +class L1Cache(RubyCache): pass def define_options(parser): return @@ -72,8 +72,8 @@ def create_system(options, full_system, system, dma_ports, ruby_system): # Only one cache exists for this protocol, so by default use the L1D # config parameters. # - cache = Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + cache = L1Cache(size = options.l1d_size, + assoc = options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. diff --git a/src/mem/ruby/structures/Cache.py b/src/mem/ruby/structures/Cache.py deleted file mode 100644 index 4eb87ac74..000000000 --- a/src/mem/ruby/structures/Cache.py +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright (c) 2009 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Steve Reinhardt -# Brad Beckmann - -from m5.params import * -from m5.proxy import * -from PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy -from m5.SimObject import SimObject - -class RubyCache(SimObject): - type = 'RubyCache' - cxx_class = 'CacheMemory' - cxx_header = "mem/ruby/structures/CacheMemory.hh" - size = Param.MemorySize("capacity in bytes"); - assoc = Param.Int(""); - replacement_policy = Param.ReplacementPolicy(PseudoLRUReplacementPolicy(), - "") - start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); - is_icache = Param.Bool(False, "is instruction only cache"); - - dataArrayBanks = Param.Int(1, "Number of banks for the data array") - tagArrayBanks = Param.Int(1, "Number of banks for the tag array") - dataAccessLatency = Param.Cycles(1, "cycles for a data array access") - tagAccessLatency = Param.Cycles(1, "cycles for a tag array access") - resourceStalls = Param.Bool(False, "stall if there is a resource failure") - ruby_system = Param.RubySystem(Parent.any, "") diff --git a/src/mem/ruby/structures/RubyCache.py b/src/mem/ruby/structures/RubyCache.py new file mode 100644 index 000000000..4eb87ac74 --- /dev/null +++ b/src/mem/ruby/structures/RubyCache.py @@ -0,0 +1,51 @@ +# Copyright (c) 2009 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt +# Brad Beckmann + +from m5.params import * +from m5.proxy import * +from PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy +from m5.SimObject import SimObject + +class RubyCache(SimObject): + type = 'RubyCache' + cxx_class = 'CacheMemory' + cxx_header = "mem/ruby/structures/CacheMemory.hh" + size = Param.MemorySize("capacity in bytes"); + assoc = Param.Int(""); + replacement_policy = Param.ReplacementPolicy(PseudoLRUReplacementPolicy(), + "") + start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); + is_icache = Param.Bool(False, "is instruction only cache"); + + dataArrayBanks = Param.Int(1, "Number of banks for the data array") + tagArrayBanks = Param.Int(1, "Number of banks for the tag array") + dataAccessLatency = Param.Cycles(1, "cycles for a data array access") + tagAccessLatency = Param.Cycles(1, "cycles for a tag array access") + resourceStalls = Param.Bool(False, "stall if there is a resource failure") + ruby_system = Param.RubySystem(Parent.any, "") diff --git a/src/mem/ruby/structures/SConscript b/src/mem/ruby/structures/SConscript index 18ab9daed..75fc6370e 100644 --- a/src/mem/ruby/structures/SConscript +++ b/src/mem/ruby/structures/SConscript @@ -33,7 +33,7 @@ Import('*') if env['PROTOCOL'] == 'None': Return() -SimObject('Cache.py') +SimObject('RubyCache.py') SimObject('DirectoryMemory.py') SimObject('LRUReplacementPolicy.py') SimObject('PseudoLRUReplacementPolicy.py')