From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 3 Aug 2020 19:24:03 +0000 (+0100)
Subject: add extra port for debug read of int regs via DMI
X-Git-Tag: semi_working_ecp5~462
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d71c0357c1cd668d56d04be94ea05b23b01beff4;p=soc.git

add extra port for debug read of int regs via DMI
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 7bcf5c9c..4fe98d3a 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -42,7 +42,8 @@ class IntRegs(RegFileArray):
                         'o1': self.write_port("dest2")} # for now (LD/ST update)
         self.r_ports = {'ra': self.read_port("src1"),
                         'rb': self.read_port("src2"),
-                        'rc': self.read_port("src3")}
+                        'rc': self.read_port("src3"),
+                        'dmi': self.read_port("dmi")} # needed for Debug (DMI)
 
 
 # Fast SPRs Regfile