From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 9 May 2019 21:33:08 +0000 (+0200)
Subject: tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)
X-Git-Tag: 24jan2021_ls180~1226
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d76a2c7db2825237e0651860e1df70dfd06fbe09;p=litex.git

tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index c8ef182b..8bae6b6b 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -124,6 +124,7 @@ class SimSoC(SoCSDRAM):
         # serial
         self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
         self.submodules.uart = uart.UART(self.uart_phy)
+        self.add_csr("uart")
         self.add_interrupt("uart")
 
         # sdram