From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 15 May 2022 18:30:49 +0000 (+0200)
Subject: set dram_clk_freq = 100.0e6 for orangecrab
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7709b941ac080905bab2943a6b5d8f660dc66a0;p=ls2.git

set dram_clk_freq = 100.0e6 for orangecrab
---

diff --git a/src/ls2.py b/src/ls2.py
index 53c3792..f1efb8f 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -876,7 +876,7 @@ def build_platform(fpga, firmware):
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
         clk_freq = 40.0e6 # 50 MHz does not work
-        ##dram_clk_freq = 80.0e6 # does not work yet (0 warnings, 2 errors)
+        dram_clk_freq = 100.0e6 # does not work yet (0 warnings, 2 errors)
 
     # merge dram_clk_freq with clk_freq if the same
     if clk_freq == dram_clk_freq: