From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Jul 2020 09:07:25 +0000 (+0100)
Subject: corrections to trap main_stage.py OP_RFID according to reading spec
X-Git-Tag: semi_working_ecp5~695
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7768aabbd433c649301acf31829b54b0617c906;p=soc.git

corrections to trap main_stage.py OP_RFID according to reading spec
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 325fb373..e5ea4cd2 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -201,9 +201,9 @@ class TrapMainStage(PipeModBase):
                 msr_check_pr(m, msr_o.data)
 
                 # hypervisor stuff
-                comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV])
-                comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) |
-                                             (~msr_i[MSR.HV] & srr1_i[MSR.HV]))
+                with m.If(msr_i[MSR.HV]):
+                    comb += msr_o.data[MSR.HV].eq(srr1_i[MSR.HV])
+                    comb += msr_o.data[MSR.ME].eq(srr1_i[MSR.ME])
                 # don't understand but it's in the spec
                 with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) |
                           (srr1_i[63-31:63-29] != Const(0b000, 3))):