From: Kamil Rakoczy Date: Fri, 10 Jul 2020 12:56:14 +0000 (+0200) Subject: Fix S/R conflicts X-Git-Tag: working-ls180~381^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d77b3305d83f6877f2177daecab658067659f4ce;p=yosys.git Fix S/R conflicts This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy --- diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 1c86c7895..b9e721415 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -742,12 +742,13 @@ module_body: module_body module_body_stmt | /* the following line makes the generate..endgenrate keywords optional */ module_body gen_stmt | + module_body ';' | /* empty */; module_body_stmt: task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | enum_decl | struct_decl | - always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';'; + always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block; checker_decl: TOK_CHECKER TOK_ID ';' {