From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 May 2020 10:33:20 +0000 (+0100)
Subject: update comment
X-Git-Tag: div_pipeline~773
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d77ea9f299398cbd12eda5b012dcecadb1927704;p=soc.git

update comment
---

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 147c891e..efeb42a9 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -43,7 +43,7 @@ class CommonOutputStage(PipeModBase):
         cr0 = Signal(4, reset_less=True)
 
         # TODO: if o[63] is XORed with "operand == OP_CMP"
-        # that can be used as a test
+        # that can be used as a test of whether to invert the +ve/-ve test
         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
 
         comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)