From: Tiago Mück <tiago.muck@arm.com>
Date: Tue, 29 Sep 2020 00:15:33 +0000 (-0500)
Subject: mem-ruby: add andMask to WriteMask
X-Git-Tag: develop-gem5-snapshot~77
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d789b75a98a9c84775cdb4bf8319045c0338104b;p=gem5.git

mem-ruby: add andMask to WriteMask

Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41154
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/ruby/common/WriteMask.hh b/src/mem/ruby/common/WriteMask.hh
index f1e5f371d..895584a5d 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020,2021 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -159,6 +159,20 @@ class WriteMask
         return true;
     }
 
+    void
+    andMask(const WriteMask & writeMask)
+    {
+        assert(mSize == writeMask.mSize);
+        for (int i = 0; i < mSize; i++) {
+            mMask[i] = (mMask.at(i)) & (writeMask.mMask.at(i));
+        }
+
+        if (writeMask.mAtomic) {
+            mAtomic = true;
+            mAtomicOp = writeMask.mAtomicOp;
+        }
+    }
+
     void
     orMask(const WriteMask & writeMask)
     {
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 1b67dc603..e48cca524 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -57,6 +57,7 @@ structure(WriteMask, external="yes", desc="...") {
   bool isEmpty();
   bool isFull();
   bool isOverlap(WriteMask);
+  void andMask(WriteMask);
   void orMask(WriteMask);
   void setInvertedMask(WriteMask);
   void fillMask();