From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Fri, 17 May 2019 21:33:13 +0000 (+0200)
Subject: rs6000: Add "enabled" attribute
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d78ba51841e429173f7a9eaa20006c04ceced29c;p=gcc.git

rs6000: Add "enabled" attribute

This adds the "enabled" attribute to the rs6000 backend.  It uses the
(new) "isa" attribute to automatically select which instruction
alternatives should be enabled.

For now it allows isa strings of "p5", "p6", "p7", meaning the
instructions introduced on that CPU, not requiring vectors; and "p7v",
"p8v", "p9v" for the same, but with vectors.

These are currently mapped to TARGET_POPCNTB, TARGET_CMPB,
TARGET_POPCNTD, TARGET_VSX, TARGET_P8_VECTOR, and TARGET_P9_VECTOR;
that will change to something a bit saner later.


	* config/rs6000/rs6000.md (isa): New attribute.
	(enabled): New attribute.

From-SVN: r271360
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 32075f689cc..988a86040a2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-17  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.md (isa): New attribute.
+	(enabled): New attribute.
+
 2019-05-17  Max Filippov  <jcmvbkbc@gmail.com>
 
 	* config/aarch64/aarch64.c (aarch64_output_mi_thunk): Call
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 31fc90a4aa2..0906ccb0167 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -265,6 +265,39 @@
    rs64a,mpccore,cell,ppca2,titan"
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
+;; The ISA we implement.
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v" (const_string "any"))
+
+;; Is this alternative enabled for the current CPU/ISA/etc.?
+(define_attr "enabled" ""
+  (cond
+    [(eq_attr "isa" "any")
+     (const_int 1)
+
+     (and (eq_attr "isa" "p5")
+	  (match_test "TARGET_POPCNTB"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p6")
+	  (match_test "TARGET_CMPB"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p7")
+	  (match_test "TARGET_POPCNTD"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p7v")
+	  (match_test "TARGET_VSX"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p8v")
+	  (match_test "TARGET_P8_VECTOR"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p9v")
+	  (match_test "TARGET_P9_VECTOR"))
+     (const_int 1)
+    ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor
 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded