From: Marek Olšák Date: Sat, 22 Sep 2018 01:01:46 +0000 (-0400) Subject: radeonsi: allow si_cp_dma_clear_buffer to clear GDS from any IB X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7a4fa91f0edfa2edd190e446447ee38e236ecfe;p=mesa.git radeonsi: allow si_cp_dma_clear_buffer to clear GDS from any IB Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 20e4f591fbb..086793637f0 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -219,8 +219,8 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, clear_value_size, coher); } else { assert(clear_value_size == 4); - si_cp_dma_clear_buffer(sctx, dst, offset, - aligned_size, *clear_value, coher, + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, dst, offset, + aligned_size, *clear_value, 0, coher, get_cache_policy(sctx, coher, size)); } diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 839b31b7fdf..33220d9f0fa 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -54,11 +54,10 @@ static inline unsigned cp_dma_max_byte_count(struct si_context *sctx) * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit * clear value. */ -static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va, - uint64_t src_va, unsigned size, unsigned flags, - enum si_cache_policy cache_policy) +static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, + uint64_t dst_va, uint64_t src_va, unsigned size, + unsigned flags, enum si_cache_policy cache_policy) { - struct radeon_cmdbuf *cs = sctx->gfx_cs; uint32_t header = 0, command = 0; assert(size <= cp_dma_max_byte_count(sctx)); @@ -146,7 +145,7 @@ void si_cp_dma_wait_for_idle(struct si_context *sctx) * DMA request, however, the CP will see the sync flag and still wait * for all DMAs to complete. */ - si_emit_cp_dma(sctx, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS); + si_emit_cp_dma(sctx, sctx->gfx_cs, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS); } static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst, @@ -207,10 +206,10 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst } } -void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, - enum si_coherency coher, - enum si_cache_policy cache_policy) +void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs, + struct pipe_resource *dst, uint64_t offset, + uint64_t size, unsigned value, unsigned user_flags, + enum si_coherency coher, enum si_cache_policy cache_policy) { struct r600_resource *rdst = r600_resource(dst); uint64_t va = (rdst ? rdst->gpu_address : 0) + offset; @@ -225,19 +224,21 @@ void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, util_range_add(&rdst->valid_buffer_range, offset, offset + size); /* Flush the caches. */ - sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | - SI_CONTEXT_CS_PARTIAL_FLUSH | - si_get_flush_flags(sctx, coher, cache_policy); + if (rdst && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) { + sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | + SI_CONTEXT_CS_PARTIAL_FLUSH | + si_get_flush_flags(sctx, coher, cache_policy); + } while (size) { unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx)); unsigned dma_flags = CP_DMA_CLEAR | (rdst ? 0 : CP_DMA_DST_IS_GDS); - si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0, coher, - &is_first, &dma_flags); + si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, user_flags, + coher, &is_first, &dma_flags); /* Emit the clear packet. */ - si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, cache_policy); + si_emit_cp_dma(sctx, cs, va, value, byte_count, dma_flags, cache_policy); size -= byte_count; va += byte_count; @@ -290,7 +291,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, coher, is_first, &dma_flags); va = sctx->scratch_buffer->gpu_address; - si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, + si_emit_cp_dma(sctx, sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, cache_policy); } @@ -373,7 +374,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, size + skipped_size + realign_size, user_flags, coher, &is_first, &dma_flags); - si_emit_cp_dma(sctx, main_dst_offset, main_src_offset, + si_emit_cp_dma(sctx, sctx->gfx_cs, main_dst_offset, main_src_offset, byte_count, dma_flags, cache_policy); size -= byte_count; @@ -389,7 +390,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, skipped_size + realign_size, user_flags, coher, &is_first, &dma_flags); - si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size, + si_emit_cp_dma(sctx, sctx->gfx_cs, dst_offset, src_offset, skipped_size, dma_flags, cache_policy); } @@ -553,11 +554,11 @@ void si_test_gds(struct si_context *sctx) src = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16); dst = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16); - si_cp_dma_clear_buffer(sctx, src, 0, 4, 0xabcdef01, SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, src, 4, 4, 0x23456789, SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, src, 8, 4, 0x87654321, SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, src, 12, 4, 0xfedcba98, SI_COHERENCY_SHADER, L2_BYPASS); - si_cp_dma_clear_buffer(sctx, dst, 0, 16, 0xdeadbeef, SI_COHERENCY_SHADER, L2_BYPASS); + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 0, 4, 0xabcdef01, 0, SI_COHERENCY_SHADER, L2_BYPASS); + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 4, 4, 0x23456789, 0, SI_COHERENCY_SHADER, L2_BYPASS); + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 8, 4, 0x87654321, 0, SI_COHERENCY_SHADER, L2_BYPASS); + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 12, 4, 0xfedcba98, 0, SI_COHERENCY_SHADER, L2_BYPASS); + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, dst, 0, 16, 0xdeadbeef, 0, SI_COHERENCY_SHADER, L2_BYPASS); si_cp_dma_copy_buffer(sctx, NULL, src, offset, 0, 16, 0, SI_COHERENCY_NONE, L2_BYPASS); si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, 0, SI_COHERENCY_NONE, L2_BYPASS); @@ -567,7 +568,7 @@ void si_test_gds(struct si_context *sctx) r[0] == 0xabcdef01 && r[1] == 0x23456789 && r[2] == 0x87654321 && r[3] == 0xfedcba98 ? "pass" : "fail"); - si_cp_dma_clear_buffer(sctx, NULL, offset, 16, 0xc1ea4146, SI_COHERENCY_NONE, L2_BYPASS); + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, NULL, offset, 16, 0xc1ea4146, 0, SI_COHERENCY_NONE, L2_BYPASS); si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, 0, SI_COHERENCY_NONE, L2_BYPASS); pipe_buffer_read(ctx, dst, 0, sizeof(r), r); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 023e0f0a0f9..3ec645f9c71 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1159,10 +1159,10 @@ void si_init_compute_blit_functions(struct si_context *sctx); SI_CPDMA_SKIP_BO_LIST_UPDATE) void si_cp_dma_wait_for_idle(struct si_context *sctx); -void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, - enum si_coherency coher, - enum si_cache_policy cache_policy); +void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs, + struct pipe_resource *dst, uint64_t offset, + uint64_t size, unsigned value, unsigned user_flags, + enum si_coherency coher, enum si_cache_policy cache_policy); void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset, unsigned size, diff --git a/src/gallium/drivers/radeonsi/si_test_dma_perf.c b/src/gallium/drivers/radeonsi/si_test_dma_perf.c index 6c04720e963..657c4ebeff8 100644 --- a/src/gallium/drivers/radeonsi/si_test_dma_perf.c +++ b/src/gallium/drivers/radeonsi/si_test_dma_perf.c @@ -181,7 +181,8 @@ void si_test_dma_perf(struct si_screen *sscreen) si_cp_dma_copy_buffer(sctx, dst, src, 0, 0, size, 0, SI_COHERENCY_NONE, cache_policy); } else { - si_cp_dma_clear_buffer(sctx, dst, 0, size, clear_value, + si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, dst, 0, size, + clear_value, 0, SI_COHERENCY_NONE, cache_policy); } } else if (test_sdma) {