From: lkcl <lkcl@web>
Date: Sat, 9 Oct 2021 10:58:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3687
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7b4e4a23838b573f41d38b7b357681b5d905016;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd/shape.mdwn b/3d_gpu/architecture/dynamic_simd/shape.mdwn
index d9cddb183..4969cf33a 100644
--- a/3d_gpu/architecture/dynamic_simd/shape.mdwn
+++ b/3d_gpu/architecture/dynamic_simd/shape.mdwn
@@ -14,4 +14,15 @@ with an example.
 The Libre-SOC IEEE754 ALUs need to be converted to SIMD Partitioning
 but without massive disruptive code-duplication or intrusive explicit
 coding as outlined in the worst of the techniques documented in
-[[dynamic_simd]]
+[[dynamic_simd]].  This in turn implies that Signals need to be declared
+for both mantissa and exponent that **change width to non-power-of-two
+sizes** depending on Partition Mask Context.
+
+Mantissa:
+
+* when the context is 1xFP64 the mantissa is 54 bits (excluding guard
+  rounding and sticky)
+* when the context is 2xFP32 there are **two** mantissas of 23 bits
+* when the context is 4xFP16 there are **four** mantissas of 10 bits
+* when the context is 4xBF16 there are four mantissas of 5 bits.
+