From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Mon, 9 Feb 2004 08:22:43 +0000 (-0800)
Subject: Add support for memory barriers.
X-Git-Tag: m5_1.0_beta2~161^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7b7363444614a4e07676151604ce9600bad1169;p=gem5.git

Add support for memory barriers.

arch/alpha/isa_desc:
    Add cache port bindings for mb & wmb.

--HG--
extra : convert_revision : 72f76150fe471d0dc97bd41598cad4d86a035e39
---

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index d4636f609..75b2f4138 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2362,8 +2362,8 @@ decode OPCODE default Unknown::unknown() {
 	    // them the same though.
 	    0x0000: trapb({{ }}, IsSerializing, No_OpClass);
 	    0x0400: excb({{ }}, IsSerializing, No_OpClass);
-	    0x4000: mb({{ }}, IsMemBarrier);
-	    0x4400: wmb({{ }}, IsWriteBarrier);
+	    0x4000: mb({{ }}, IsMemBarrier, RdPort);
+	    0x4400: wmb({{ }}, IsWriteBarrier, WrPort);
 	}
 
 #ifdef FULL_SYSTEM