From: lkcl <lkcl@web>
Date: Thu, 16 Jun 2022 21:53:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1746
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7b8b41f9b98caef484880296dfe9a4571cbf959;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 803932c34..90628f751 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -11,6 +11,7 @@ See links:
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 * old page [[simple_v_extension/specification/sv.setvl]]
 * [[sv/svstep]]
+* pseudocode [[openower/isa/simplev]]
 
 Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]♧