From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Jan 2024 19:24:22 +0000 (+0000)
Subject: fix ISACaller BA/BB vector read
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7bb8e30b70119968205535bc0f082b0f1f9361c;p=openpower-isa.git

fix ISACaller BA/BB vector read
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 8e828d07..bd106897 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -555,8 +555,9 @@ def get_cr_in(dec2, name):
     sv_override = yield dec2.dec_cr_in.sv_override
     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
     in1 = yield dec2.e.read_cr1.data
+    in2 = yield dec2.e.read_cr2.data
     cr_isvec = yield dec2.cr_in_isvec
-    log("get_cr_in", in_sel, CROutSel.CR0.value, in1, cr_isvec)
+    log("get_cr_in", name, in_sel, CROutSel.CR0.value, in1, in2, cr_isvec)
     log("    sv_cr_in", sv_cr_in)
     log("    cr_bf", in_bitfield)
     log("    spec", spec)
@@ -565,9 +566,12 @@ def get_cr_in(dec2, name):
     if name == 'BI':
         if in_sel == CRInSel.BI.value:
             return in1, cr_isvec
-    if name in ['BA', 'BB']:
+    if name == 'BA':
         if in_sel == CRInSel.BA_BB.value:
             return in1, cr_isvec
+    if name == 'BB':
+        if in_sel == CRInSel.BA_BB.value:
+            return in2, cr_isvec
     if name == 'BFA':
         if in_sel == CRInSel.BFA.value:
             return in1, cr_isvec