From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 17 Jan 2021 15:59:22 +0000 (+0100)
Subject: cleanup test_issuer_mmu_data_path.py
X-Git-Tag: 24jan2021_ls180~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7c6c5e7b014e187ca7537e6d56a25809bee137f;p=soc.git

cleanup test_issuer_mmu_data_path.py
---

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 31925c3f..88d9b6b1 100644
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -8,15 +8,21 @@ from soc.fu.test.common import (
     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
 
 # this test case takes about half a minute to run on my Talos II
-class MMUDataPathTestCase(TestAccumulatorBase):
+class MMUTestCase(TestAccumulatorBase):
     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
     # libre-soc has own SPR unit
     # other instructions here -> must be load/store
 
     def case_mfspr_after_invalid_load(self):
-        lst = [ 
-                "tlbie 0,0,0,0,0",    # RB,RS,RIC,PRS,R
-                "dcbz 1,2"
+        lst = [
+                "dcbz 1,2",
+                "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
+                #"mfspr 1, 18",     # DSISR to reg 1
+                #"mfspr 2, 19",     # DAR to reg 2
+                #"mtspr 18, 1",
+                #"mtspr 19, 2",
+                #test ldst instructions
+                "lhz 3, 0(1)" # lhz RT,D(RA) -> this should go through the mmu
               ]
 
         initial_regs = [0] * 32
@@ -30,7 +36,6 @@ class MMUDataPathTestCase(TestAccumulatorBase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(TestRunner(MMUDataPathTestCase().test_data,microwatt_mmu=True))
-
+    suite.addTest(TestRunner(MMUTestCase().test_data,microwatt_mmu=True))
     runner = unittest.TextTestRunner()
     runner.run(suite)