From: lkcl <lkcl@web>
Date: Fri, 25 Dec 2020 23:50:30 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~872
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7d05e941f93754fa9c2f0ff764e2f430b066f0f;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 1ebcb9257..237140d71 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -7,6 +7,8 @@
 This document provides an overview and introduction as to why SV (a
 Cray-style Vector augmentation to OpenPOWER) exists, and how it works.
 
+# Introduction: SIMD and Cray Vectors
+
 SIMD, the primary method for easy parallelism of the
 past 30 years in Computer Architectures, is [known to be
 harmful](https://www.sigarch.org/simd-instructions-considered-harmful/).
@@ -33,6 +35,8 @@ abstract to a Scalar ISA, in the process allowing register file size
 increases using "tagging" (similar to how x86 originally extended
 registers from 32 to 64 bit).
 
+## SV
+
 The fundamentals are:
 
 * The Program Counter gains a "Sub Counter" context.