From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 30 Sep 2020 20:45:21 +0000 (+0000)
Subject: increase core.size to 27500x27500
X-Git-Tag: partial-core-ls180-gdsii~55
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7e142de755f2ab823215c2b450843bbfb272ee9;p=soclayout.git

increase core.size to 27500x27500
---

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
index 027853c..f06c681 100644
--- a/experiments9/coriolis2/ioring.py
+++ b/experiments9/coriolis2/ioring.py
@@ -187,7 +187,7 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
           'pads.west'       : pw,
             #[ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
           # core option (big, time-consuming)
-          #'core.size'       : ( l(26000), l(26000) ),
+          #'core.size'       : ( l(27500), l(27500) ),
           #'chip.size'       : ( l(30000), l(30000) ),
           # no-core option (test_issuer but no actual core)
           'core.size'       : ( l(13000), l(13000) ),