From: Luke Kenneth Casson Leighton Date: Thu, 26 Sep 2019 03:40:25 +0000 (+0100) Subject: add RADV X-Git-Tag: convert-csv-opcode-to-binary~3964 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7e1c2ab1697fcc827e0242255934c791f61202b;p=libreriscv.git add RADV --- diff --git a/nlnet_2019_amdvlk_port.mdwn b/nlnet_2019_amdvlk_port.mdwn index 6a804b86c..cd6a389b9 100644 --- a/nlnet_2019_amdvlk_port.mdwn +++ b/nlnet_2019_amdvlk_port.mdwn @@ -158,6 +158,10 @@ efforts to introduce "mainline" LLVM patches on an ongoing piecemeal basis, and at the same time *add our own assembler back-end* into the same fast-moving target. +Whereas with RADV it is upstreamed in MESA, and has much wider community +support, it will need very careful detailed evaluation to ensure that it meets +the needs of the Libre RISC-V Vector Engine. + ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes? As mentioned in the 2018 submission, the Libre RISC-V