From: Tobias Platen Date: Wed, 6 Jan 2021 18:26:52 +0000 (+0100) Subject: fu/mmu/fsm.py: mfspr!=mtspr X-Git-Tag: 24jan2021_ls180~37 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d7f14911dad1b430d39bfaa448596b94e44dd282;p=soc.git fu/mmu/fsm.py: mfspr!=mtspr --- diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 690a1c04..5cce2dde 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -185,7 +185,7 @@ class FSMMMUStage(ControlBase): # blip the MMU and wait for it to complete comb += valid.eq(1) # start "pulse" comb += l_in.valid.eq(blip) # start - comb += l_in.mtspr.eq(1) # mtspr mode + comb += l_in.mtspr.eq(0) # mfspr!=mtspr comb += l_in.sprn.eq(spr) # which SPR comb += l_in.rs.eq(a_i) # incoming operand (RS) comb += o.data.eq(l_out.sprval) # SPR from MMU