From: whitequark <cz@m-labs.hk>
Date: Tue, 9 Jul 2019 19:28:09 +0000 (+0000)
Subject: back.verilog: run proc_prune for much cleaner output.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d80594fd881d7ef3dc682ecaa29fbc27439c28e5;p=nmigen.git

back.verilog: run proc_prune for much cleaner output.

This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.
---

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index cb099c9..444e124 100644
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -36,6 +36,7 @@ def convert(*args, strip_src=False, **kwargs):
 read_ilang <<rtlil
 {}
 rtlil
+proc_prune
 proc_init
 proc_arst
 proc_dff