From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 17 Jun 2019 22:10:33 +0000 (-0700)
Subject: Cleanup
X-Git-Tag: working-ls180~881^2^2~294
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d80678e581899315791706ee1703bf700b0f9c15;p=yosys.git

Cleanup
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 776bceb3b..f56350b1d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -527,7 +527,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			}
 			RTLIL::Module* box_module = design->module(cell->type);
 			if (box_module && box_module->attributes.count("\\abc_box_id"))
-				boxes.emplace_back(it->second);
+				boxes.emplace_back(cell);
 			++it;
 		}
 
@@ -629,8 +629,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			}
 		}
 
-                for (auto cell : boxes)
-                        module->remove(cell);
+		for (auto cell : boxes)
+			module->remove(cell);
 
 		// Copy connections (and rename) from mapped_mod to module
 		for (auto conn : mapped_mod->connections()) {