From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 26 Jun 2022 21:56:01 +0000 (+0100)
Subject: make svstep output srcstep/dststep, basically viota
X-Git-Tag: sv_maxu_works-initial~312
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d80a18d2f4744df529902f4f8f845c382c723fe5;p=openpower-isa.git

make svstep output srcstep/dststep, basically viota
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 16fbaa1b..04e8cd5c 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1769,9 +1769,15 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         self.allow_next_step_inc = submode.value + 1
         log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
         self.svstate_next_mode = mode
-        if self.svstate_next_mode > 0:
+        if self.svstate_next_mode > 0 and self.svstate_next_mode < 5:
             shape_idx = self.svstate_next_mode.value-1
             return SelectableInt(self.remap_idxs[shape_idx], 7)
+        if self.svstate_next_mode == 5:
+            self.svstate_next_mode = 0
+            return SelectableInt(self.svstate.srcstep, 7)
+        if self.svstate_next_mode == 6:
+            self.svstate_next_mode = 0
+            return SelectableInt(self.svstate.dststep, 7)
         return SelectableInt(0, 7)
 
     def svstate_pre_inc(self):
diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index fe8ffd98..1372dda3 100644
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -576,6 +576,45 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(svstate.mo1, 3)
             self.assertEqual(svstate.RMpst, 1)
 
+    def test_svstep_iota(self):
+        """tests svstep "straight", placing srcstep, dststep into vector
+        """
+        lst = SVP64Asm(["setvl 1, 0, 4, 0, 1, 1",
+                        "sv.svstep 0.v, 5, 1", # svstep get vector srcstep
+                        "sv.svstep. 4.v, 6, 1", # svstep get vector dststep
+                        ])
+        lst = list(lst)
+
+        # SVSTATE
+        svstate = SVP64State()
+        #svstate.vl = 2 # VL
+        #svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate)
+            print ("SVSTATE after", bin(sim.svstate.asint()))
+            print ("        vl", bin(sim.svstate.vl))
+            print ("        mvl", bin(sim.svstate.maxvl))
+            print ("    srcstep", bin(sim.svstate.srcstep))
+            print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate. vfirst))
+            self.assertEqual(sim.svstate.vl, 4)
+            self.assertEqual(sim.svstate.maxvl, 4)
+            # svstep called four times, reset occurs, srcstep zero
+            self.assertEqual(sim.svstate.srcstep, 0)
+            self.assertEqual(sim.svstate.dststep, 0)
+            for i in range(4):
+                self.assertEqual(sim.gpr(0+i), SelectableInt(i, 64))
+                self.assertEqual(sim.gpr(4+i), SelectableInt(i, 64))
+            self.assertEqual(sim.svstate.vfirst, 0)
+            CR0 = sim.crl[0]
+            print("      CR0", bin(CR0.get_range().value))
+            self.assertEqual(CR0[CRFields.EQ], 0)
+            self.assertEqual(CR0[CRFields.LT], 0)
+            self.assertEqual(CR0[CRFields.GT], 0)
+            self.assertEqual(CR0[CRFields.SO], 1)
+
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None):
         if initial_regs is None: