From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 May 2020 19:56:08 +0000 (+0100)
Subject: whitespace cleanup
X-Git-Tag: div_pipeline~962
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8132b5efa033068df6c805ee295415ecbcc68fe;p=soc.git

whitespace cleanup
---

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 98d10cfa..7240ebe5 100644
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -86,7 +86,7 @@ class CRMainStage(PipeModBase):
                 ba = Signal(2, reset_less=True)
                 bb = Signal(2, reset_less=True)
 
-                # Stupid bit ordering stuff
+                # Stupid bit ordering stuff.  Because POWER.
                 comb += bt.eq(3-BT[0:2])
                 comb += ba.eq(3-BA[0:2])
                 comb += bb.eq(3-BB[0:2])