From: Gabriel Somlo Date: Mon, 3 Aug 2020 18:40:45 +0000 (-0400) Subject: integration/soc: make DMA slave region cover (at least) the lower 4GB X-Git-Tag: 24jan2021_ls180~36^2~3 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8161e5a861318cf236353d39f36442dc462e450;p=litex.git integration/soc: make DMA slave region cover (at least) the lower 4GB Assuming we currently support a 32-bit (4GB) physical address space, ensure that the dma_bus slave covers the entire range, covering any possible layout of the LiteX SoC memory map (e.g., rocket has MMIO in a wide range of registers located below 2GB, and DRAM starting at the 2GB mark, needing DMA accesses to be routed appropriately for the entire 4GB physical address range). Signed-off-by: Gabriel Somlo --- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 40ae46a5..4a459ed1 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -845,7 +845,7 @@ class SoC(Module): data_width = self.bus.data_width, ) dma_bus = wishbone.Interface(data_width=self.bus.data_width) - self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x80000000)) # FIXME: size + self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus) # Connect SoCController's reset to CPU reset