From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 28 Dec 2013 09:29:22 +0000 (+0100)
Subject: More conservastive $eq/$ne/$eqx/$nex opt_const code
X-Git-Tag: yosys-0.2.0~219
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d81e3ed3aeca4b517736b8c95b20b2e8b1e0c860;p=yosys.git

More conservastive $eq/$ne/$eqx/$nex opt_const code
---

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index a3f3ee418..84285567e 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -160,19 +160,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 			assert(a.chunks.size() == b.chunks.size());
 			for (size_t i = 0; i < a.chunks.size(); i++) {
-				if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL &&
-						a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0]) {
+				if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0] &&
+						a.chunks[i].data.bits[0] <= RTLIL::State::S1 && b.chunks[i].data.bits[0] <= RTLIL::State::S1) {
 					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(module, cell, "empty", "\\Y", new_y);
 					goto next_cell;
 				}
-				if (cell->type == "$eq" || cell->type == "$ne") {
-					if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
-						continue;
-					if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
-						continue;
-				}
 				if (a.chunks[i] == b.chunks[i])
 					continue;
 				new_a.append(a.chunks[i]);