From: Samuel Iglesias Gonsálvez Date: Fri, 17 Mar 2017 10:57:25 +0000 (+0100) Subject: i965/vec4/dce: improve track of partial flag register writes X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8441e2276912d353d4fc6c0cf6b781ab5153ee7;p=mesa.git i965/vec4/dce: improve track of partial flag register writes This is required for correctness in presence of multiple 4-wide flag writes (e.g. 4-wide instructions with a conditional mod set) which update a different portion of the same 8-bit flag subregister. Right now we keep track of flag dataflow with 8-bit granularity and consider flag writes to have killed any previous definition of the same subregister even if the write was less than 8 channels wide, which can cause live flag register updates to be dead code-eliminated incorrectly. Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Francisco Jerez --- diff --git a/src/intel/compiler/brw_vec4_dead_code_eliminate.cpp b/src/intel/compiler/brw_vec4_dead_code_eliminate.cpp index 5b22a096dd1..c09a3d7ebe9 100644 --- a/src/intel/compiler/brw_vec4_dead_code_eliminate.cpp +++ b/src/intel/compiler/brw_vec4_dead_code_eliminate.cpp @@ -121,7 +121,7 @@ vec4_visitor::dead_code_eliminate() } } - if (inst->writes_flag() && !inst->predicate) { + if (inst->writes_flag() && !inst->predicate && inst->exec_size == 8) { for (unsigned c = 0; c < 4; c++) BITSET_CLEAR(flag_live, c); }