From: Eric Anholt Date: Thu, 17 Nov 2011 22:45:54 +0000 (-0800) Subject: i965: Base HW depth format setup based on MESA_FORMAT, not bpp. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d84a180417d1eabd680554970f1eaaa93abcd41e;p=mesa.git i965: Base HW depth format setup based on MESA_FORMAT, not bpp. This will make handling new formats (like actually exposing Z32F) easier and more reliable. v2: Remove the check for hiz buffer -- the MESA_FORMAT should really be giving us the value we want even for hiz. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index cb1405ca866..8a6ee708ccf 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -197,6 +197,37 @@ const struct brw_tracked_state brw_psp_urb_cbs = { .emit = upload_psp_urb_cbs, }; +uint32_t +brw_depthbuffer_format(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &intel->ctx; + struct gl_framebuffer *fb = ctx->DrawBuffer; + struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); + struct intel_renderbuffer *srb; + + if (!drb && + (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) && + srb->Base.Format == MESA_FORMAT_S8_Z24) { + drb = srb; + } + + switch (drb->Base.Format) { + case MESA_FORMAT_Z16: + return BRW_DEPTHFORMAT_D16_UNORM; + case MESA_FORMAT_Z32_FLOAT: + return BRW_DEPTHFORMAT_D32_FLOAT; + case MESA_FORMAT_X8_Z24: + return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; + case MESA_FORMAT_S8_Z24: + return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; + default: + _mesa_problem(ctx, "Unexpected depth format %s\n", + _mesa_get_format_name(drb->Base.Format)); + return BRW_DEPTHFORMAT_D16_UNORM; + } +} + static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; @@ -309,29 +340,11 @@ static void emit_depthbuffer(struct brw_context *brw) } else { struct intel_region *region = depth_irb->mt->region; - unsigned int format; uint32_t tile_x, tile_y, offset; /* If using separate stencil, hiz must be enabled. */ assert(!stencil_irb || hiz_region); - switch (region->cpp) { - case 2: - format = BRW_DEPTHFORMAT_D16_UNORM; - break; - case 4: - if (intel->depth_buffer_is_float) - format = BRW_DEPTHFORMAT_D32_FLOAT; - else if (hiz_region) - format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; - else - format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; - break; - default: - assert(0); - return; - } - offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y); assert(intel->gen < 6 || region->tiling == I915_TILING_Y); @@ -340,7 +353,7 @@ static void emit_depthbuffer(struct brw_context *brw) BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | - (format << 18) | + (brw_depthbuffer_format(brw) << 18) | ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */ ((hiz_region ? 1 : 0) << 22) | /* hiz enable */ (BRW_TILEWALK_YMAJOR << 26) | diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 2157ffd37e8..59fe81aec26 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -121,6 +121,11 @@ extern const struct brw_tracked_state gen7_wm_constant_surface; extern const struct brw_tracked_state gen7_wm_state; extern const struct brw_tracked_state gen7_wm_surfaces; +/* brw_misc_state.c */ +uint32_t +brw_depthbuffer_format(struct brw_context *brw); + + /*********************************************************************** * brw_state.c */ @@ -198,8 +203,4 @@ uint32_t get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset, int fs_attr, bool two_side_color); -/* gen7_misc_state.c */ -unsigned int -gen7_depth_format(struct brw_context *brw); - #endif diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 25e1b1d0fe1..c50cd30ec13 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -29,34 +29,6 @@ #include "brw_state.h" #include "brw_defines.h" -unsigned int -gen7_depth_format(struct brw_context *brw) -{ - struct intel_context *intel = &brw->intel; - struct gl_context *ctx = &intel->ctx; - struct gl_framebuffer *fb = ctx->DrawBuffer; - struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); - struct intel_region *region = NULL; - - if (drb) - region = drb->mt->region; - else - return BRW_DEPTHFORMAT_D32_FLOAT; - - switch (region->cpp) { - case 2: - return BRW_DEPTHFORMAT_D16_UNORM; - case 4: - if (intel->depth_buffer_is_float) - return BRW_DEPTHFORMAT_D32_FLOAT; - else - return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; - default: - assert(!"Should not get here."); - } - return 0; -} - static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; @@ -110,7 +82,7 @@ static void emit_depthbuffer(struct brw_context *brw) BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | - (gen7_depth_format(brw) << 18) | + (brw_depthbuffer_format(brw) << 18) | (0 << 22) /* no HiZ buffer */ | ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) | ((ctx->Depth.Mask != 0) << 28) | diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index d3ffbd39b4b..8876722812d 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -154,7 +154,7 @@ upload_sf_state(struct brw_context *brw) dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE; /* _NEW_BUFFERS */ - dw1 |= (gen7_depth_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); + dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); /* _NEW_POLYGON */ if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo) diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index d49255b44a2..ca01120db6f 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -281,7 +281,6 @@ struct intel_context bool hw_stencil; bool hw_stipple; - bool depth_buffer_is_float; bool no_rast; bool always_flush_batch; bool always_flush_cache;