From: Florent Kermarrec Date: Mon, 19 Jan 2015 16:52:05 +0000 (+0100) Subject: clean up X-Git-Tag: 24jan2021_ls180~2572^2~48 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d84ae7c80c4992329ecb871fbaf94e470424323b;p=litex.git clean up --- diff --git a/Makefile b/Makefile deleted file mode 100644 index 5a3406d1..00000000 --- a/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -MSCDIR = ../misoc -CURDIR = ../lite-sata -PYTHON = python3 -TOOLCHAIN = vivado -PROGRAMMER = vivado - -CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -Op programmer $(PROGRAMMER) -t bist_kc705 - -csv: - cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv -Ot export_mila True - cd $(CURDIR) - -bit: - cd $(MSCDIR) && $(CMD) build-bitstream - cd $(CURDIR) - -build: csv bit - -load: - cd $(MSCDIR) && $(CMD) load-bitstream - cd $(CURDIR) - -test: - cd test && $(PYTHON) test_regs.py - cd $(CURDIR) - -all: build load test - -.PHONY: load test all diff --git a/litesata/common.py b/litesata/common.py index 99c5d214..90f7c23c 100644 --- a/litesata/common.py +++ b/litesata/common.py @@ -13,6 +13,12 @@ from migen.actorlib.fifo import * from migen.actorlib.structuring import Pipeline, Converter # PHY / Link Layers +frequencies = { + "SATA3" : 150.0, + "SATA2" : 75.0, + "SATA1" : 37.5, +} + primitives = { "ALIGN" : 0x7B4A4ABC, "CONT" : 0X9999AA7C, diff --git a/litesata/phy/__init__.py b/litesata/phy/__init__.py index fcb206f3..58fb1f04 100644 --- a/litesata/phy/__init__.py +++ b/litesata/phy/__init__.py @@ -3,14 +3,14 @@ from litesata.phy.ctrl import * from litesata.phy.datapath import * class LiteSATAPHY(Module): - def __init__(self, device, pads, speed, clk_freq): - self.speed = speed + def __init__(self, device, pads, revision, clk_freq): + self.revision = revision # Transceiver / Clocks if device[:3] == "xc7": # Kintex 7 from litesata.phy.k7.trx import K7LiteSATAPHYTRX from litesata.phy.k7.crg import K7LiteSATAPHYCRG - self.trx = K7LiteSATAPHYTRX(pads, speed) - self.crg = K7LiteSATAPHYCRG(pads, self.trx, speed, clk_freq) + self.trx = K7LiteSATAPHYTRX(pads, revision) + self.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq) else: msg = "Device" + device + "not (yet) supported." raise NotImplementedError(msg) diff --git a/litesata/phy/k7/crg.py b/litesata/phy/k7/crg.py index 9bfc67eb..c3267c6c 100644 --- a/litesata/phy/k7/crg.py +++ b/litesata/phy/k7/crg.py @@ -1,7 +1,7 @@ from litesata.common import * class K7LiteSATAPHYCRG(Module): - def __init__(self, pads, gtx, speed, clk_freq): + def __init__(self, pads, gtx, revision, clk_freq): self.reset = Signal() self.ready = Signal() @@ -34,7 +34,7 @@ class K7LiteSATAPHYCRG(Module): "SATA2" : 8.0, "SATA3" : 4.0 } - mmcm_div = mmcm_div_config[speed] + mmcm_div = mmcm_div_config[revision] self.specials += [ Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i), Instance("MMCME2_ADV", diff --git a/litesata/phy/k7/trx.py b/litesata/phy/k7/trx.py index ad9a9c83..14a3b14e 100644 --- a/litesata/phy/k7/trx.py +++ b/litesata/phy/k7/trx.py @@ -18,7 +18,7 @@ class _RisingEdge(Module): self.comb += o.eq(i & ~i_d) class K7LiteSATAPHYTRX(Module): - def __init__(self, pads, speed): + def __init__(self, pads, revision): # Common signals # control @@ -105,15 +105,15 @@ class K7LiteSATAPHYTRX(Module): "SATA2" : 2, "SATA3" : 1 } - rxout_div = div_config[speed] - txout_div = div_config[speed] + rxout_div = div_config[revision] + txout_div = div_config[revision] cdr_config = { "SATA1" : 0x0380008BFF40100008, "SATA2" : 0x0388008BFF40200008, "SATA3" : 0X0380008BFF10200010 } - rxcdr_cfg = cdr_config[speed] + rxcdr_cfg = cdr_config[revision] # Specific / Generic signals encoding/decoding self.comb += [ diff --git a/make.py b/make.py index 7f4a1cf8..28112e48 100644 --- a/make.py +++ b/make.py @@ -8,6 +8,8 @@ from migen.fhdl import simplify from misoclib.gensoc import cpuif +from litesata.common import * + def _import(default, name): return importlib.import_module(default + "." + name) @@ -29,7 +31,7 @@ load-bitstream load bitstream into volatile storage. all clean, build-csr-csv, build-bitstream, load-bitstream. """) - parser.add_argument("-t", "--target", default="bist_kc705", help="Core type to build") + parser.add_argument("-t", "--target", default="bist", help="Core type to build") parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build") parser.add_argument("-p", "--platform", default=None, help="platform to build for") parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option") @@ -77,21 +79,34 @@ if __name__ == "__main__": print(" "+a) sys.exit(1) - print("""\ -# __ _ __ _______ _________ -# / / (_) /____ / __/ _ /_ __/ _ | -# / /__/ / __/ -_)\ \/ __ |/ / / __ | -# /____/_/\__/\__/___/_/ |_/_/ /_/ |_| -# -# a generic and configurable SATA core -# based on Migen/MiSoC -# -#====== Building options: ====== -# SATA revision: {} -# Integrated BIST: {} -# Integrated Logic Analyzer: {} -# Crossbar ports: {} -#===============================""".format(soc.sata_phy.speed, hasattr(soc.sata, "bist"), hasattr(soc, "mila"), len(soc.sata.crossbar.slaves))) + + revision = soc.sata_phy.revision + frequency = frequencies[soc.sata_phy.revision] + has_bist = hasattr(soc.sata, "bist") + has_crossbar = hasattr(soc.sata, "crossbar") + ports = 1 if not has_crossbar else len(soc.sata.crossbar.slaves) + + print(""" + __ _ __ _______ _________ + / / (_) /____ / __/ _ /_ __/ _ | + / /__/ / __/ -_)\ \/ __ |/ / / __ | + /____/_/\__/\__/___/_/ |_/_/ /_/ |_| + +A small footprint and configurable SATA core + based on Migen/MiSoC + +====== Building options: ====== +SATA revision: {} / {} MHz +BIST: {} +Crossbar: {} +Ports: {} +===============================""".format( + revision, frequency, + has_bist, + has_crossbar, + ports + ) +) # dependencies if actions["all"]: diff --git a/targets/__init__.py b/targets/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/targets/bist.py b/targets/bist.py new file mode 100644 index 00000000..648df127 --- /dev/null +++ b/targets/bist.py @@ -0,0 +1,219 @@ +import os + +from litesata.common import * +from migen.bank import csrgen +from migen.bus import wishbone, csr +from migen.bus import wishbone2csr +from migen.genlib.cdc import * +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.bank.description import * + +from misoclib import identifier + +from miscope import MiLa, Term, UART2Wishbone + +from litesata.common import * +from litesata.phy import LiteSATAPHY +from litesata import LiteSATA + +class _CRG(Module): + def __init__(self, platform): + self.cd_sys = ClockDomain() + self.reset = Signal() + + clk200 = platform.request("clk200") + clk200_se = Signal() + self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se) + + pll_locked = Signal() + pll_fb = Signal() + pll_sys = Signal() + self.specials += [ + Instance("PLLE2_BASE", + p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, + + # VCO @ 1GHz + p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, + p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, + i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, + + # 166MHz + p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, + + p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=, + + p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=, + + p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=, + + p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4= + ), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), + AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset), + ] + +class GenSoC(Module): + csr_base = 0x00000000 + csr_data_width = 32 + csr_map = { + "uart2wb": 0, + "identifier": 2, + } + interrupt_map = {} + cpu_type = None + def __init__(self, platform, clk_freq): + # UART <--> Wishbone bridge + self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600) + + # CSR bridge 0x00000000 (shadow @0x00000000) + self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) + self._wb_masters = [self.uart2wb.wishbone] + self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] + self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) + + # CSR + self.identifier = identifier.Identifier(0, int(clk_freq), 0) + + def add_cpu_memory_region(self, name, origin, length): + self.cpu_memory_regions.append((name, origin, length)) + + def add_cpu_csr_region(self, name, origin, busword, obj): + self.cpu_csr_regions.append((name, origin, busword, obj)) + + def do_finalize(self): + # Wishbone + self.wishbonecon = wishbone.InterconnectShared(self._wb_masters, + self._wb_slaves, register=True) + + # CSR + self.csrbankarray = csrgen.BankArray(self, + lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], + data_width=self.csr_data_width) + self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) + for name, csrs, mapaddr, rmap in self.csrbankarray.banks: + self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) + for name, memory, mapaddr, mmap in self.csrbankarray.srams: + self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) + +class BISTLeds(Module): + def __init__(self, platform, sata_phy): + # 1Hz blinking leds (sata_rx and sata_tx clocks) + sata_rx_led = platform.request("user_led", 0) + sata_tx_led = platform.request("user_led", 1) + + sata_rx_cnt = Signal(32) + sata_tx_cnt = Signal(32) + + sata_freq = int(frequencies[sata_phy.revision]*1000*1000) + + self.sync.sata_rx += \ + If(sata_rx_cnt == 0, + sata_rx_led.eq(~sata_rx_led), + sata_rx_cnt.eq(sata_freq//2) + ).Else( + sata_rx_cnt.eq(sata_rx_cnt-1) + ) + + self.sync.sata_tx += \ + If(sata_tx_cnt == 0, + sata_tx_led.eq(~sata_tx_led), + sata_tx_cnt.eq(sata_freq//2) + ).Else( + sata_tx_cnt.eq(sata_tx_cnt-1) + ) + + # ready leds (crg and ctrl) + self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready) + self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready) + +class BISTSoC(GenSoC, AutoCSR): + default_platform = "kc705" + csr_map = { + "sata": 10, + } + csr_map.update(GenSoC.csr_map) + + def __init__(self, platform, export_mila=False): + clk_freq = 166*1000000 + GenSoC.__init__(self, platform, clk_freq) + self.crg = _CRG(platform) + + # SATA PHY/Core/Frontend + self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata0"), "SATA2", clk_freq) + self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME + self.sata = LiteSATA(self.sata_phy, with_crossbar=True, with_bist=True, with_bist_csr=True) + + # Status Leds + self.leds = BISTLeds(platform, self.sata_phy) + +class BISTSoCDevel(BISTSoC, AutoCSR): + csr_map = { + "mila": 11 + } + csr_map.update(BISTSoC.csr_map) + def __init__(self, platform, export_mila=False): + BISTSoC.__init__(self, platform, export_mila) + + self.sata_core_link_rx_fsm_state = Signal(4) + self.sata_core_link_tx_fsm_state = Signal(4) + self.sata_core_transport_rx_fsm_state = Signal(4) + self.sata_core_transport_tx_fsm_state = Signal(4) + self.sata_core_command_rx_fsm_state = Signal(4) + self.sata_core_command_tx_fsm_state = Signal(4) + + debug = ( + self.sata_phy.ctrl.ready, + + self.sata_phy.source.stb, + self.sata_phy.source.data, + self.sata_phy.source.charisk, + + self.sata_phy.sink.stb, + self.sata_phy.sink.data, + self.sata_phy.sink.charisk, + + self.sata.core.command.sink.stb, + self.sata.core.command.sink.sop, + self.sata.core.command.sink.eop, + self.sata.core.command.sink.ack, + self.sata.core.command.sink.write, + self.sata.core.command.sink.read, + self.sata.core.command.sink.identify, + + self.sata.core.command.source.stb, + self.sata.core.command.source.sop, + self.sata.core.command.source.eop, + self.sata.core.command.source.ack, + self.sata.core.command.source.write, + self.sata.core.command.source.read, + self.sata.core.command.source.identify, + self.sata.core.command.source.success, + self.sata.core.command.source.failed, + self.sata.core.command.source.data, + + self.sata_core_link_rx_fsm_state, + self.sata_core_link_tx_fsm_state, + self.sata_core_transport_rx_fsm_state, + self.sata_core_transport_tx_fsm_state, + self.sata_core_command_rx_fsm_state, + self.sata_core_command_tx_fsm_state, + ) + + self.mila = MiLa(depth=2048, dat=Cat(*debug)) + self.mila.add_port(Term) + if export_mila: + mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv") + self.mila.export(self, debug, mila_filename) + + def do_finalize(self): + BISTSoC.do_finalize(self) + self.comb += [ + self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state), + self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state), + self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state), + self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state), + self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state), + self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state) + ] + +default_subtarget = BISTSoC diff --git a/targets/bist_kc705.py b/targets/bist_kc705.py deleted file mode 100644 index 3818ba8b..00000000 --- a/targets/bist_kc705.py +++ /dev/null @@ -1,224 +0,0 @@ -import os - -from litesata.common import * -from migen.bank import csrgen -from migen.bus import wishbone, csr -from migen.bus import wishbone2csr -from migen.genlib.cdc import * -from migen.genlib.resetsync import AsyncResetSynchronizer -from migen.bank.description import * - -from misoclib import identifier - -from miscope import MiLa, Term, UART2Wishbone - -from litesata.common import * -from litesata.phy import LiteSATAPHY -from litesata import LiteSATA - -class _CRG(Module): - def __init__(self, platform): - self.cd_sys = ClockDomain() - self.reset = Signal() - - clk200 = platform.request("clk200") - clk200_se = Signal() - self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se) - - pll_locked = Signal() - pll_fb = Signal() - pll_sys = Signal() - self.specials += [ - Instance("PLLE2_BASE", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - - # VCO @ 1GHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, - p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, - i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, - - # 166MHz - p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, - - p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=, - - p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=, - - p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=, - - p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4= - ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset), - ] - -class GenSoC(Module): - csr_base = 0x00000000 - csr_data_width = 32 - csr_map = { - "uart2wb": 0, - "identifier": 2, - } - interrupt_map = {} - cpu_type = None - def __init__(self, platform, clk_freq): - # UART <--> Wishbone bridge - self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600) - - # CSR bridge 0x00000000 (shadow @0x00000000) - self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) - self._wb_masters = [self.uart2wb.wishbone] - self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] - self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) - - # CSR - self.identifier = identifier.Identifier(0, int(clk_freq), 0) - - def add_cpu_memory_region(self, name, origin, length): - self.cpu_memory_regions.append((name, origin, length)) - - def add_cpu_csr_region(self, name, origin, busword, obj): - self.cpu_csr_regions.append((name, origin, busword, obj)) - - def do_finalize(self): - # Wishbone - self.wishbonecon = wishbone.InterconnectShared(self._wb_masters, - self._wb_slaves, register=True) - - # CSR - self.csrbankarray = csrgen.BankArray(self, - lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], - data_width=self.csr_data_width) - self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) - for name, csrs, mapaddr, rmap in self.csrbankarray.banks: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) - for name, memory, mapaddr, mmap in self.csrbankarray.srams: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) - -class BISTLeds(Module): - def __init__(self, platform, sata_phy): - # 1Hz blinking leds (sata_rx and sata_tx clocks) - sata_rx_led = platform.request("user_led", 0) - sata_tx_led = platform.request("user_led", 1) - - sata_rx_cnt = Signal(32) - sata_tx_cnt = Signal(32) - - sata_freqs_mhz = { - "SATA3" : 150.0, - "SATA2" : 75.0, - "SATA1" : 37.5, - } - sata_freq = int(sata_freqs_mhz[sata_phy.speed]*1000*1000) - - self.sync.sata_rx += \ - If(sata_rx_cnt == 0, - sata_rx_led.eq(~sata_rx_led), - sata_rx_cnt.eq(sata_freq//2) - ).Else( - sata_rx_cnt.eq(sata_rx_cnt-1) - ) - - self.sync.sata_tx += \ - If(sata_tx_cnt == 0, - sata_tx_led.eq(~sata_tx_led), - sata_tx_cnt.eq(sata_freq//2) - ).Else( - sata_tx_cnt.eq(sata_tx_cnt-1) - ) - - # ready leds (crg and ctrl) - self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready) - self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready) - -class BISTSoC(GenSoC, AutoCSR): - default_platform = "kc705" - csr_map = { - "sata": 10, - } - csr_map.update(GenSoC.csr_map) - - def __init__(self, platform, export_mila=False): - clk_freq = 166*1000000 - GenSoC.__init__(self, platform, clk_freq) - self.crg = _CRG(platform) - - # SATA PHY/Core/Frontend - self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata0"), "SATA2", clk_freq) - self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME - self.sata = LiteSATA(self.sata_phy, with_crossbar=True, with_bist=True, with_bist_csr=True) - - # Status Leds - self.leds = BISTLeds(platform, self.sata_phy) - -class BISTSoCDevel(BISTSoC, AutoCSR): - csr_map = { - "mila": 11 - } - csr_map.update(BISTSoC.csr_map) - def __init__(self, platform, export_mila=False): - BISTSoC.__init__(self, platform, export_mila) - - self.sata_core_link_rx_fsm_state = Signal(4) - self.sata_core_link_tx_fsm_state = Signal(4) - self.sata_core_transport_rx_fsm_state = Signal(4) - self.sata_core_transport_tx_fsm_state = Signal(4) - self.sata_core_command_rx_fsm_state = Signal(4) - self.sata_core_command_tx_fsm_state = Signal(4) - - debug = ( - self.sata_phy.ctrl.ready, - - self.sata_phy.source.stb, - self.sata_phy.source.data, - self.sata_phy.source.charisk, - - self.sata_phy.sink.stb, - self.sata_phy.sink.data, - self.sata_phy.sink.charisk, - - self.sata.core.command.sink.stb, - self.sata.core.command.sink.sop, - self.sata.core.command.sink.eop, - self.sata.core.command.sink.ack, - self.sata.core.command.sink.write, - self.sata.core.command.sink.read, - self.sata.core.command.sink.identify, - - self.sata.core.command.source.stb, - self.sata.core.command.source.sop, - self.sata.core.command.source.eop, - self.sata.core.command.source.ack, - self.sata.core.command.source.write, - self.sata.core.command.source.read, - self.sata.core.command.source.identify, - self.sata.core.command.source.success, - self.sata.core.command.source.failed, - self.sata.core.command.source.data, - - self.sata_core_link_rx_fsm_state, - self.sata_core_link_tx_fsm_state, - self.sata_core_transport_rx_fsm_state, - self.sata_core_transport_tx_fsm_state, - self.sata_core_command_rx_fsm_state, - self.sata_core_command_tx_fsm_state, - ) - - self.mila = MiLa(depth=2048, dat=Cat(*debug)) - self.mila.add_port(Term) - if export_mila: - mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv") - self.mila.export(self, debug, mila_filename) - - def do_finalize(self): - BISTSoC.do_finalize(self) - self.comb += [ - self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state), - self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state), - self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state), - self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state), - self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state), - self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state) - ] - -default_subtarget = BISTSoC