From: lkcl <lkcl@web>
Date: Sat, 3 Sep 2022 12:19:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~710
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8512783b9d854a8279bc732d678095084ad1937;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 59f00316d..3cd27a037 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -668,19 +668,19 @@ Dimensions are calculated exactly as `svindex`. `rmm` and
 `mm` are as per `svindex`.  
 
 *Programmer's Note: offsets for `svshape2` may be specified in the range
-0-7. Given that the principle of Simple-V is to fit on top of
+0-15. Given that the principle of Simple-V is to fit on top of
 byte-addressable register files and that GPR and FPR are 64-bit (8 bytes)
 it should be clear that the offset may, when `elwidth=8`, begin an
 element-level operation starting element zero at any arbitrary byte.
-On cursory examination attempting to go **beyond** the range 0-7 seems
-inadequate until it is recalled that the **next GPR or FPR** is an
+On cursory examination attempting to go beyond the range 0-7 seems
+unnecessary given that the **next GPR or FPR** is an
 alias for an offset in the range 8-15.  Thus by simply increasing
 the starting Vector point of the operation to the next register it
 can be seen that the offset of 0-7 would be sufficient.  Unfortunately
-however some operations are EXTRA2-encoded which does in fact leave
-them inaccessible.  TODO: decide if the decision to sacrifice one
-bit of `offs` in favour of an `inv` bit is worth it.
-<https://bugs.libre-soc.org/show_bug.cgi?id=911#c9>*
+however some operations are EXTRA2-encoded it is **not possible**
+to increase the GPR/FPR register number by one, because EXTRA2-encoding
+of GPR/FPR Vector numbers are restricted to even numbering. The
+additional offset range (8-15) helps overcome this limitation.*
 
 # TODO