From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 16 Oct 2014 15:42:24 +0000 (+0200)
Subject: use new direct access on endpoints
X-Git-Tag: 24jan2021_ls180~2575^2~52
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d860813dec5af4d2ba38c329cdc368a74c7165b1;p=litex.git

use new direct access on endpoints
---

diff --git a/miscope/uart2wishbone.py b/miscope/uart2wishbone.py
index 9f61693d..b697f51f 100644
--- a/miscope/uart2wishbone.py
+++ b/miscope/uart2wishbone.py
@@ -95,15 +95,15 @@ class UART2Wishbone(Module, AutoCSR):
 		cmd = Signal(8)
 		fsm.act("WAIT_CMD",
 			If(uart.rx.source.stb,
-				If(	(uart.rx.source.payload.d == self.WRITE_CMD) |
-					(uart.rx.source.payload.d == self.READ_CMD),
+				If(	(uart.rx.source.d == self.WRITE_CMD) |
+					(uart.rx.source.d == self.READ_CMD),
 					NextState("RECEIVE_BURST_LENGTH")
 				),
 			word_cnt.clr.eq(1),
 			burst_cnt.clr.eq(1)
 			)
 		)
-		self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.payload.d))
+		self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.d))
 
 		####
 		burst_length = Signal(8)
@@ -115,7 +115,7 @@ class UART2Wishbone(Module, AutoCSR):
 			)
 		)
 		self.sync += \
-			If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.payload.d))
+			If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.d))
 
 		####
 		address = Signal(32)
@@ -132,7 +132,7 @@ class UART2Wishbone(Module, AutoCSR):
 		)
 		self.sync += \
 			If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.source.stb,
-					address.eq(Cat(uart.rx.source.payload.d, address[0:24]))
+					address.eq(Cat(uart.rx.source.d, address[0:24]))
 			)
 
 		###
@@ -189,13 +189,13 @@ class UART2Wishbone(Module, AutoCSR):
 				)
 			),
 			uart.tx.sink.stb.eq(1),
-			chooser(data, word_cnt.value, uart.tx.sink.payload.d, n=4, reverse=True)
+			chooser(data, word_cnt.value, uart.tx.sink.d, n=4, reverse=True)
 		)
 
 		###
 		self.sync += \
 			If(fsm.ongoing("RECEIVE_DATA") & uart.rx.source.stb,
-				data.eq(Cat(uart.rx.source.payload.d, data[0:24]))
+				data.eq(Cat(uart.rx.source.d, data[0:24]))
 			).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
 				data.eq(self.wishbone.dat_r)
 			)