From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 21 Feb 2021 19:20:17 +0000 (+0000)
Subject: add CR out vector detection to PowerDecoder2 no_out_vec
X-Git-Tag: convert-csv-opcode-to-binary~173
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d86ba356371cdfd66b6c96f9fccc0ad4c8d5d87a;p=soc.git

add CR out vector detection to PowerDecoder2 no_out_vec
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 2372888f..8a6ef221 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -1180,7 +1180,8 @@ class PowerDecode2(PowerDecodeSubset):
         comb += self.o_isvec.eq(o_svdec.isvec)
         comb += self.o2_isvec.eq(o2_svdec.isvec)
         # TODO: include SPRs and CRs here!  must be True when *all* are scalar
-        comb += self.no_out_vec.eq((~o2_svdec.isvec) & (~o_svdec.isvec))
+        comb += self.no_out_vec.eq((~o2_svdec.isvec) & (~o_svdec.isvec) &
+                                   (crout_svdec.isvec))
 
         # SPRs out
         comb += e.read_spr1.eq(dec_a.spr_out)