From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 19 Apr 2009 10:17:14 +0000 (-0700)
Subject: X86: Implement the load machine status word instruction (LMSW).
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152;p=gem5.git

X86: Implement the load machine status word instruction (LMSW).
---

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 0f6d59f3d..e55756fec 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -126,7 +126,7 @@
                             0x7: invlpga();
                         }
                         0x4: smsw_Rv();
-                        0x6: lmsw_Rv();
+                        0x6: Inst::LMSW(Rv);
                         0x7: decode MODRM_RM {
                             0x0: Inst::SWAPGS();
                             0x1: rdtscp();
@@ -156,7 +156,7 @@
                             }
                         }
                         0x4: smsw_Mw();
-                        0x6: lmsw_Mw();
+                        0x6: Inst::LMSW(Mw);
                         0x7: Inst::INVLPG(M);
                         default: Inst::UD2();
                     }
diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index 902c01abb..c09cdf6e8 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -32,4 +32,40 @@ def macroop CLTS {
     andi t1, t1, 0xF7, dataSize=1
     wrcr 0, t1, dataSize=8
 };
+
+def macroop LMSW_R {
+    rdcr t1, 0, dataSize=8
+    # This logic sets MP, EM, and TS to whatever is in the operand. It will
+    # set PE but not clear it.
+    limm t2, "~ULL(0xe)", dataSize=8
+    and t1, t1, t2, dataSize=8
+    andi t2, reg, 0xf, dataSize=8
+    or t1, t1, t2, dataSize=8
+    wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_M {
+    ld t3, seg, sib, disp, dataSize=2
+    rdcr t1, 0, dataSize=8
+    # This logic sets MP, EM, and TS to whatever is in the operand. It will
+    # set PE but not clear it.
+    limm t2, "~ULL(0xe)", dataSize=8
+    and t1, t1, t2, dataSize=8
+    andi t2, t3, 0xf, dataSize=8
+    or t1, t1, t2, dataSize=8
+    wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_P {
+    rdip t7, dataSize=asz
+    ld t3, seg, riprel, disp, dataSize=2
+    rdcr t1, 0, dataSize=8
+    # This logic sets MP, EM, and TS to whatever is in the operand. It will
+    # set PE but not clear it.
+    limm t2, "~ULL(0xe)", dataSize=8
+    and t1, t1, t2, dataSize=8
+    andi t2, t3, 0xf, dataSize=8
+    or t1, t1, t2, dataSize=8
+    wrcr 0, t1, dataSize=8
+};
 '''