From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 18:26:30 +0000 (-0800)
Subject: Add testcase
X-Git-Tag: working-ls180~818^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d86d073ad657b5bc92b8ef020b79c070333f267f;p=yosys.git

Add testcase
---

diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys
new file mode 100644
index 000000000..a29c29df6
--- /dev/null
+++ b/tests/opt/opt_merge_init.ys
@@ -0,0 +1,49 @@
+read_verilog -icells <<EOT
+module top(input clk, i, (* init = 1'b0 *) output o, p);
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ffo  (
+    .CLK(clk),
+    .D(i),
+    .Q(o)
+  );
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ffp  (
+    .CLK(clk),
+    .D(i),
+    .Q(p)
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 1 a:init=1'0
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ff1  (
+    .CLK(clk),
+    .D(i),
+    .Q(o[1])
+  );
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ff0  (
+    .CLK(clk),
+    .D(i),
+    .Q(o[0])
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 1 a:init=2'bx1