From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 May 2019 08:52:14 +0000 (+0100)
Subject: whoops disconnected go_wr from CUs by mistake
X-Git-Tag: div_pipeline~1978
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d888bf3415f6aca6aa31148445065dc89f0c5ce2;p=soc.git

whoops disconnected go_wr from CUs by mistake
---

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 662ebec3..74489360 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -48,7 +48,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.go_wr_i = Signal(reset_less=True) # go write in
         self.issue_i = Signal(reset_less=True) # fn issue in
         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
-        self.go_die_i = Signal(reset_less=True) # go die (reset)
+        self.go_die_i = Signal() # go die (reset)
 
         self.oper_i = Signal(opwid, reset_less=True) # opcode in
         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
@@ -69,8 +69,10 @@ class ComputationUnitNoDelay(Elaboratable):
         # shadow/go_die
         reset_w = Signal(reset_less=True)
         reset_r = Signal(reset_less=True)
-        m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
-        m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
+        #m.d.comb += reset_w.eq(self.go_wr_i)# | self.go_die_i)
+        #m.d.comb += reset_r.eq(self.go_rd_i)# | self.go_die_i)
+        reset_w = self.go_wr_i
+        reset_r = self.go_rd_i
 
         # This is fascinating and very important to observe that this
         # is in effect a "3-way revolving door".  At no time may all 3
@@ -109,7 +111,7 @@ class ComputationUnitNoDelay(Elaboratable):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):
             # write req release out.  waits until shadow is dropped.
-            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q & self.shadown_i)
+            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q)# & self.shadown_i)
 
         # create a latch/register for src1/src2
         latchregister(m, self.src1_i, self.alu.a, src_l.q)
diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 53eea0d5..dc067472 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -81,8 +81,9 @@ class CompUnits(Elaboratable):
         m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
         m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l))
         m.d.comb += self.busy_o.eq(Cat(*busy_l))
-        #m.d.comb += Cat(*godie_l).eq(self.go_die_i)
-        #m.d.comb += Cat(*shadow_l).eq(self.shadown_i)
+        m.d.comb += Cat(*godie_l).eq(self.go_die_i)
+        m.d.comb += Cat(*shadow_l).eq(self.shadown_i)
+        m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
         m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
         m.d.comb += Cat(*issue_l).eq(self.issue_i)
 
@@ -212,6 +213,7 @@ class Scoreboard(Elaboratable):
         n_int_alus = 4
         m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
         m.d.comb += cu.shadown_i.eq(-1)
+        m.d.comb += cu.go_die_i.eq(0)
 
         # Int FUs
         m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)