From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 19:03:25 +0000 (-0700)
Subject: Cleanup xilinx_dsp
X-Git-Tag: working-ls180~1039^2~55
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d88903e6108f8afc8e74ee3d3e942b98c21e1ae9;p=yosys.git

Cleanup xilinx_dsp
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 0ee230ccc..7d34c6a78 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,7 @@ pattern xilinx_dsp_pack
 
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigBit> clock
-state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP
+state <SigSpec> sigA sigB sigC sigD sigM sigP
 state <IdString> postAddAB postAddMuxAB
 state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol
 state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol