From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Sep 2018 04:35:10 +0000 (+0100)
Subject: assign SV REG CSRs (using new union ability)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d88a7c1700397abab309250bdbb8ceadb1cbc249;p=riscv-isa-sim.git

assign SV REG CSRs (using new union ability)
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0ad4e3e..7d95c49 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -354,7 +354,26 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_SVREGCFG5:
     case CSR_SVREGCFG6:
     case CSR_SVREGCFG7:
+    {
+      // identify which (pair) of SV config CAM registers are being set
+      int tbidx = (which - CSR_SVREGCFG0) * 2;
+      // lower 16 bits go into even, upper into odd...
+      state.sv_csrs[tbidx].u = get_field(val, 0xffff);
+      state.sv_csrs[tbidx+1].u = get_field(val, 0xffff0000);
+      // clear out all CSRs above the one(s) being set: this ensures that
+      // when it comes to context-switching, it's clear what needs to be saved
+      for (int i = tbidx+2; i < 16; i++)
+      {
+          state.sv_csrs[i].u = 0;
+      }
+      // okaaay and now "unpack" the CAM to make it easier to use.  this
+      // approach is not designed to be efficient right now.  optimise later
+      for (int i = 0; i < SV_CSR_SZ; i++)
+      {
+        // TODO
+      }
       break;
+    }
 #endif
     case CSR_FFLAGS:
       dirty_fp_state;